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document number: 314054-002 dual-core intel ? itanium ? processor 9000 and 9100 series dual-core intel ? itanium ? processor 1.6 ghz with 24 mb l3 cache 9050 dual-core intel ? itanium ? processor 1.6 ghz with 18 mb l3 cache 9040 dual-core intel ? itanium ? processor 1.6 ghz with 8 mb l3 cache 9030 dual-core intel ? itanium ? processor 1.42 ghz with 12 mb l3 cache 9020 dual-core intel ? itanium ? processor 1.4 ghz with 12 mb l3 cache 9015 intel ? itanium ? processor 1.6 ghz with 6 mb l3 cache 9010 dual-core intel? itanium? processor 1.66/1.6 ghz with 24 mb l3 cache 9152 dual-core intel ? itanium ? processor 1.66 ghz with 24 mb l3 cache 9150m dual-core intel ? itanium ? processor 1.6 ghz with 24 mb l3 cache 9150n dual-core intel ? itanium ? processor 1.66 ghz with 18 mb l3 cache 9140m dual-core intel ? itanium ? processor 1.6 ghz with 18 mb l3 cache 9140n dual-core intel ? itanium ? processor 1.42 ghz with 12 mb l3 cache 9120n dual-core intel ? itanium ? processor 1.66 ghz with 8 mb l3 cache 9130m intel ? itanium ? processor 1.6 ghz with 12 mb l3 cache 9110n datasheet october 2007
2 dual-core intel ? itanium ? processor 9000 and 9100 series datasheet information in this document is pr ovided in connection with intel ? products. no license, express or implied, by estoppel or otherwise, to any intellectual proper ty rights is granted by this document. except as provided in intel's terms and condit ions of sale for such products, intel assumes no liability whatsoever, and intel disclaims any express or implied warranty, rela ting to sale and/or use of intel products including liability or warranties relating to fitness for a particul ar purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. intel products are not intended for use in medical, life saving, life sustaining applications. intel may make changes to specifications and product descriptions at any time, without notice. designers must not rely on the absence or characteristics of any features or instructions marked ?reserved? or ?undefined.? int el reserves these for future definition and shall have no responsib ility whatsoever for conflicts or incompatibilities arising fro m future changes to them the dual-core intel ? itanium ? 9000 and 9100 series processor may contain design defects or errors known as errata which may cause the product to deviate from published specifications. current characterized errata are available on request. contact your local intel sales office or your distributor to obta in the latest specifications an d before placing your product o rder. copies of documents which have an order number and are referenced in this document, or other intel literature, may be obtained by calling1-800-548-4725, or by visiting in tel's website at http://www.intel.com. intel, itanium, and the intel logo are trademarks or registered trademarks of in tel corporation or its subsidiaries in the unit ed states and other countries. copyright ? 2002-2007, intel corporation *other names and brands may be cl aimed as the property of others. i2c is a two-wire communication bus /protocol developed by phillips. smbus is a subset of the i2c bus/protocol developed by int el. implementation of the i2c bus/protocol or the smbus bus/protocol may require licenses from vari ous entities, including phillips electronics, n.v. and north american phillips corporation.
dual-core intel ? itanium ? processor 9000 and 9100 series datasheet 3 contents 1 introduction............................................................................................................... 11 1.1 overview ......................................................................................................... 11 1.2 processor abstraction layer ................................................................................ 11 1.3 mixing processors of different frequencies an d cache sizes .................................... 12 1.4 terminology ..................................................................................................... 12 1.5 state of data .................................................................................................... 12 1.6 reference documents ........................................................................................ 13 2 electrical specifications ............................................................................................... 15 2.1 dual-core intel ? itanium ? processor 9000 and 9100 series system bus .................. 15 2.1.1 system bus power pins ........................................................................ 15 2.1.2 system bus no connect ....................................................................... 15 2.2 system bus signals ........................................................................................... 15 2.2.1 signal groups ..................................................................................... 15 2.2.2 signal descriptions .............................................................................. 17 2.3 package specifications ....................................................................................... 18 2.4 signal specifications .......................................................................................... 18 2.4.1 maximum ratings ................................................................................ 22 2.5 system bus signal quality specifications and measurement guidelines ..................... 23 2.5.1 overshoot/undershoot magnitude .......................................................... 23 2.5.2 overshoot/undershoot pulse duration .................................................... 24 2.5.3 activity factor..................................................................................... 24 2.5.4 reading overshoot/undershoot specificat ion tables ................................. 24 2.5.5 determining if a system meets the overshoot/undershoot specifications...................................................................................... 25 2.5.6 wired-or signals ................................................................................ 25 2.6 voltage regulator connector signals................ .................................................... 27 2.7 system bus clock and processor clocking........... .................................................. 31 2.8 recommended connections for unused pins.......................................................... 33 3 pinout specifications ................................................................................................... 35 4 mechanical specifications............................................................................................. 65 4.1 processor package dimensions ............................................................................ 65 4.1.1 voltage regulator (mvr) to processor package interface........................... 71 4.2 package marking ............................................................................................... 72 4.2.1 processor top-side marking .................................................................. 72 4.2.2 processor bottom-side marking ............................................................. 73 5 thermal specifications ................................................................................................ 75 5.1 thermal features .............................................................................................. 75 5.1.1 thermal alert...................................................................................... 75 5.1.2 enhanced thermal management ............................................................ 76 5.1.3 power trip .......................................................................................... 76 5.1.4 thermal trip ....................................................................................... 76 5.2 case temperature ............................................................................................. 76 6 system management feature specifications ................................................................... 79 6.1 system management bus ................................................................................... 79 6.1.1 system management bus interface ........................................................ 79 6.1.2 system management interface signals ................................................... 79 6.1.3 smbus device addressing ..................................................................... 81 6.2 processor information rom ................................................................................ 82 6.3 scratch eeprom ............................................................................................... 85
4 dual-core intel ? itanium ? processor 9000 and 9100 series datasheet 6.4 processor information rom and scratch eeprom supported smbus transactions .....................................................................................................85 6.5 thermal sensing device .....................................................................................86 6.6 thermal sensing device supported smbus transa ctions..........................................87 6.7 thermal sensing device registers........................................................................88 6.7.1 thermal reference registers .................................................................88 6.7.2 thermal limit registers ........................................................................89 6.7.3 status register ....................................................................................89 6.7.4 configuration register ..........................................................................89 6.7.5 conversion rate register ......................................................................90 a signals reference .......................................................................................................91 a.1 alphabetical signals reference ............................................................................91 a.1.1 a[49:3]# (i/o).......................................................................................91 a.1.2 a20m# (i) .............................................................................................91 a.1.3 ads# (i/o)............................................................................................91 a.1.4 ap[1:0]# (i/o).......................................................................................91 a.1.5 asz[1:0]# (i/o).....................................................................................91 a.1.6 attr[3:0]# (i/o) ...................................................................................92 a.1.7 bclkp/bclkn (i) ....................................................................................92 a.1.8 be[7:0]# (i/o).......................................................................................92 a.1.9 berr# (i/o) ..........................................................................................93 a.1.10 binit# (i/o)..........................................................................................94 a.1.11 bnr# (i/o)............................................................................................94 a.1.12 bpm[5:0]# (i/o) ....................................................................................94 a.1.13 bpri# (i) ..............................................................................................94 a.1.14 br[0]# (i/o) and br[3:1]# (i).................................................................94 a.1.15 breq[3:0]# (i/o)...................................................................................95 a.1.16 ccl# (i/o) ............................................................................................96 a.1.17 cpupres# (o) .......................................................................................96 a.1.18 d[127:0]# (i/o).....................................................................................96 a.1.19 d/c# (i/o) ............................................................................................96 a.1.20 dbsy# (i/o) ..........................................................................................96 a.1.21 dbsy_c1# (o) .......................................................................................96 a.1.22 dbsy_c2# (o) .......................................................................................96 a.1.23 defer# (i) ............................................................................................96 a.1.24 den# (i/o)............................................................................................97 a.1.25 dep[15:0]# (i/o) ...................................................................................97 a.1.26 dhit# (i) ..............................................................................................97 a.1.27 dps# (i/o) ............................................................................................98 a.1.28 drdy# (i/o)..........................................................................................98 a.1.29 drdy_c1# (o).......................................................................................98 a.1.30 drdy_c2# (o).......................................................................................98 a.1.31 dsz[1:0]# (i/o) ....................................................................................98 a.1.32 exf[4:0]# (i/o) .....................................................................................98 a.1.33 fcl# (i/o) ............................................................................................99 a.1.34 ferr# (o).............................................................................................99 a.1.35 gseq# (i) .............................................................................................99 a.1.36 hit# (i/o) and hitm# (i/o) ....................................................................99 a.1.37 id[9:0]# (i) ..........................................................................................99 a.1.38 ids# (i)................................................................................................99 a.1.39 ignne# (i)............................................................................................99 a.1.40 init# (i) ...............................................................................................99 a.1.41 int (i) ................................................................................................ 100 a.1.42 ip[1:0]# (i) ......................................................................................... 100 a.1.43 len[2:0]# (i/o) ................................................................................... 100 a.1.44 lint[1:0] (i) ....................................................................................... 100
dual-core intel ? itanium ? processor 9000 and 9100 series datasheet 5 a.1.45 lock# (i/o)........................................................................................ 100 a.1.46 nmi (i) ............................................................................................... 101 a.1.47 own# (i/o) ........................................................................................ 101 a.1.48 pmi# (i) ............................................................................................. 101 a.1.49 pwrgood (i) ...................................................................................... 101 a.1.50 req[5:0]# (i/o) .................................................................................. 101 a.1.51 reset# (i) ......................................................................................... 102 a.1.52 rp# (i/o) ........................................................................................... 102 a.1.53 rs[2:0]# (i) ....................................................................................... 103 a.1.54 rsp# (i) ............................................................................................. 103 a.1.55 sbsy# (i/o)........................................................................................ 103 a.1.56 sbsy_c1# (o)..................................................................................... 103 a.1.57 sbsy_c2# (o)..................................................................................... 103 a.1.58 splck# (i/o) ...................................................................................... 103 a.1.59 stbn[7:0]# and stbp[7:0]# (i/o) ......................................................... 103 a.1.60 tck (i) ............................................................................................... 104 a.1.61 tdi (i)................................................................................................ 104 a.1.62 tdo (o).............................................................................................. 104 a.1.63 thrmtrip# (o) ................................................................................... 104 a.1.64 thrmalert# (o)................................................................................. 104 a.1.65 tms (i) ............................................................................................... 104 a.1.66 tnd# (i/o) ......................................................................................... 104 a.1.67 trdy# (i) ........................................................................................... 105 a.1.68 trst# (i) ........................................................................................... 105 a.1.69 wsnp# (i/o)....................................................................................... 105 a.2 signal summaries ........................................................................................... 105 figures 2-1 generic clock waveform .................................................................................... 21 2-2 smsc clock waveform ....................................................................................... 22 2-3 system bus signal waveform exhibiting overshoot/undershoot............................... 23 2-4 processors power tab physical layout .................................................................. 28 2-5 system bus reset and configuration timings for cold reset.................................... 31 2-6 system bus reset and configuration timings for warm reset ................................. 32 3-1 dual-core intel ? itanium ? processor 9000 and 9100 series pinout.......................... 35 4-1 processor package............................................................................................. 66 4-2 package height and pin dimensions ..................................................................... 67 4-3 processor package mechanical interface dimensions .............................................. 69 4-4 processor package top-side components height dimensions .................................. 70 4-5 processor package bottom-side components height dimensions ............................. 70 4-6 processor to mvr interface loads ........................................................................ 71 4-7 processor top-side marking on ihs ..................................................................... 73 4-8 processor bottom-side marking placement on interposer ........................................ 74 5-1 dual-core intel ? itanium ? processor 9000 and 9100 series thermal features .......................................................................................................... 75 5-2 itanium ? processor package thermocouple location.............................................. 77 6-1 logical schematic of smbus circuitry ............ ....................................................... 80
6 dual-core intel ? itanium ? processor 9000 and 9100 series datasheet tables 2-1 itanium ? processor system bus signal groups ......................................................16 2-2 nominal resistance values for tuner1, tuner2, and tuner3 .....................................17 2-3 processor package specifications .........................................................................18 2-4 agtl+ signals dc specifications..........................................................................19 2-5 power good signal dc specifications .............. ......................................................19 2-6 system bus clock differential hstl dc specifications .............................................19 2-7 tap connection dc specifications .................. ......................................................19 2-8 smbus dc specifications.....................................................................................20 2-9 lvttl signal dc specifications ............................................................................20 2-10 system bus clock differential hstl ac specific ations .............................................20 2-11 smbus ac specifications .....................................................................................21 2-12 dual-core intel ? itanium ? processor absolute maximum ratings.............................22 2-13 source synchronous agtl+ signal group and wired-or signal group absolute overshoot/undershoot tolerance ............................................................25 2-14 source synchronous agtl+ signal group time-dependent overshoot/ undershoot tolerance for 400-mhz system bus .....................................................26 2-15 wired-or signal group (binit#, hit#, hitm#, bnr#, tnd#, berr#) overshoot/undershoot tolerance for 400-mhz system bus......................................26 2-16 source synchronous agtl+ signal group time-dependent overshoot/ undershoot tolerance for 533-mhz system bus .....................................................26 2-17 wired-or signal group (binit#, hit#, hitm#, bnr#, tnd#, berr#) overshoot/undershoot tolerance for 533-mhz system bus......................................27 2-18 vr connector signals .........................................................................................27 2-19 power connector pinouts ....................................................................................28 2-20 processors core voltage identification code (vcore and vcache) ...........................30 2-21 connection for unused pins .................................................................................33 2-22 tuner1/tuner3 translation table.......................................................................34 3-1 pin/signal information sorted by pin name ...........................................................36 3-2 pin/signal information sorted by pin location... .....................................................50 4-1 processor package dimensions ............................................................................67 4-2 processor package mechanical interface dimensio ns...............................................68 4-3 processor package load limits at power tab .... .....................................................71 5-1 case temperature specification ...................... .....................................................77 6-1 system management interface signal description s .................................................79 6-2 thermal sensing device smbus addressing on the dual-core intel ? itanium ? processor 9000 and 9100 series.............................................................81 6-3 eeprom smbus addressing on the dual-core intel ? itanium ? processor 9000 and 9100 series ........................................................................................82 6-4 processor information rom format ......................................................................82 6-5 current address read smbus packet ....................................................................85 6-6 random address read smbus packet ...................................................................86 6-7 byte write smbus packet ....................................................................................86 6-8 write byte smbus packet ....................................................................................87 6-9 read byte smbus packet ....................................................................................87 6-10 send byte smbus packet ....................................................................................87 6-11 receive byte smbus packet.................................................................................87 6-12 ara smbus packet .............................................................................................87 6-13 command byte bit assignment ............................................................................88 6-14 thermal sensing device status register .......... .....................................................89 6-15 thermal sensing device configuration register. .....................................................89 6-16 thermal sensing device conversion rate regist er..................................................90
dual-core intel ? itanium ? processor 9000 and 9100 series datasheet 7 a-1 address space size ........................................................................................... 92 a-2 effective memory type signal encoding ................................................................ 92 a-3 special transaction encoding on byte enables ....................................................... 93 a-5 br0# (i/o), br1#, br2#, br3# signals for 2p rotating interconnect ...................... 95 a-4 br0# (i/o), br1#, br2#, br3# signals for 4p rotating interconnect ...................... 95 a-6 br[3:0]# signals and agent ids ......................................................................... 95 a-7 did[9:0]# encoding .......................................................................................... 97 a-8 extended function signals ........................... ....................................................... 98 a-9 length of data transfers .................................................................................. 100 a-10 transaction types defined by reqa#/reqb# signals ........................................... 102 a-11 stbp[7:0]# and stbn[7:0]# associations .......................................................... 104 a-12 output signals ................................................................................................ 105 a-13 input signals .................................................................................................. 105 a-14 input/output signals (single driver) .................................................................. 106 a-15 input/output signals (multiple driver)........... ..................................................... 107
8 dual-core intel ? itanium ? processor 9000 and 9100 series datasheet revision history document number revision number description date 314054 -002 ? updated with 9100 series product info rmation; updated brand name from ?itanium 2? to ?itanium?. october 2007 314054 -001 ? initial release of the document. july 2006
dual-core intel ? itanium ? processor 9000 and 9100 series datasheet 9 dual-core intel ? itanium ? processor 9000 and 9100 series dual-core intel ? itanium ? processor 1.6 ghz with 24 mb l3 cache 9050 dual-core intel ? itanium ? processor 1.6 ghz with 18 mb l3 cache 9040 dual-core intel ? itanium ? processor 1.6 ghz with 8 mb l3 cache 9030 dual-core intel ? itanium ? processor 1.42 ghz with 12 mb l3 cache 9020 dual-core intel ? itanium ? processor 1.4 ghz with 12 mb l3 cache 9015 intel ? itanium ? processor 1.6 ghz with 6 mb l3 cache 9010 dual-core intel ? itanium ? processor 1.66 ghz with 24 mb l3 cache 9150m dual-core intel ? itanium ? processor 1.6 ghz with 24 mb l3 cache 9150n dual-core intel ? itanium ? processor 1.66 ghz with 18 mb l3 cache 9140m dual-core intel ? itanium ? processor 1.6 ghz with 18 mb l3 cache 9140n dual-core intel ? itanium ? processor 1.42 ghz with 12 mb l3 cache 9120n dual-core intel ? itanium ? processor 1.66 ghz with 8 mb l3 cache 9130m intel ? itanium ? processor 1.6 ghz with 12 mb l3 cache 9110n product features ? dual core ? two complete 64-bit processing cores on one processor. ? epic (explicitly parallel instruction computing) technology for current and future requir ements of high-end enterprise an d technical workloads ? provide a variety of advanced implementations of para llelism, predication, and speculation, resulting in superior instruction-level parallelism (ilp). ? hyper-threading technology ? two times the number of os threads per core provided by earlier single-thread implementations. ? wide, parallel hardwa re based on intel ? itanium ? architecture for high performance: ? integrated on-die l3 cache of up to 24mb; cache hints for l1, l2, and l3 caches for reduced memory latency. ? 128 general and 128 floating-point registers supporting register rotation. ? register stack engine for effective management of processor resources. ? support for predication and speculation. ? extensive ras features for business-critical applications: ? full smbus compatibility. ? enhanced machine check architecture with extensive ecc and parity protection. ? enhanced thermal management. ? built-in processor information rom (pirom). ?built-in programmable eeprom. ? socket level lockstep ? core level lockstep ? intel ? virtualization technology for virtualization for data-intensive applications. ? reduces virtualization complexity. ? improves virtualization performance. ? increases operating system compatibility. ? intel ? cache safe technology ensures mainframe- caliber availability. ? minimize l3 cache errors. ? outstanding energy efficiency. ? 20 percent less power than previous intel itanium processor. ? 2.5 times higher pe rformance per watt. ? high-bandwidth system bus for multiprocessor scalability: ? up to 8.53gb/s bandwidth. ? 128-bit wide data bus. ? 50-bits of physical memory addressing and 64-bits of virtual addressing. ? up to four physical processors on the same system bus at 400-mhz or 533-mhz data bus frequency. ? expandable to systems with multiple system buses. ? features to support flexible platform environments: ? ia-32 execution layer supports ia-32 application binaries. ? bi-endian support. ? processor abstraction layer eliminates processor dependencies. ? 667-mhz, 1.66-ghz, 3-load bus a ? this feature enables increased bandwidth for enterprise and hpc. ? demand based switching (dbs) a ? provides additional power management capability. a. this feature is applicable to only the 9100 series processors
10 dual-core intel ? itanium ? processor 9000 and 9100 series datasheet the dual-core intel ? itanium ? processor 9000 and 9100 series delivers new levels of flexibility, reliability, performance, and cost-effective scalab ility for your most data-intensive business and technical applications. with double the performanc e of previous intel itanium processors, the dual- core intel itanium processor 9000 and 9100 series pr ovides more reasons than ever to migrate your business-critical applications off risc and mainframe systems and onto cost-effective intel architecture servers. the dual-core intel itanium processor 9000 and 9100 series provides close to triple the amount of l3 cache (24 megabyte s), hyper-threading technology for increased performance, intel ? virtualization technology for improved virtualization, intel ? cache safe technology for increased availability, and 20 percent lower power consumption. dual-core itanium ? -based systems are available from leading oems worldwide and run popular 64- bit operating systems such as microsoft* windows server* 2003; linux* from suse, red hat, red flag, and other distributions; hp nonstop*; open vms*; and hp-ux*. more th an 7,000 applications are available for itanium-based systems, from vendor s such as microsoft, bea, ibm, ansys, gaussian, symantec/veritas, oracle, sap, and sas. and wi th industry support growing and future intel itanium processor family advances already in development, your itanium-based server investment will continue to deliver performance advances an d savings for your most demanding applications.
dual-core intel ? itanium ? processor 9000 and 9100 series datasheet 11 introduction 1 introduction 1.1 overview the dual-core intel itanium processor 9000 an d 9100 series employs explicitly parallel instruction computing (epic) design concepts for a tighter coupling between hardware and software. in this design style, the in terface between hardware and software is engineered to enable the software to exploit all available compile-time information and efficiently deliver this information to the hardware. it addresses several fundamental performance bottlenecks in modern computers, such as memory latency, memory address disambiguation, and control flow de pendencies. the epic constructs provide powerful architectural semantics and enable the software to make global optimizations across a large scheduling scope, thereby exposing available instruction level parallelism (ilp) to the hardware. the hardware takes advantage of this enhanced ilp, and provides abundant execution resources. additionally, it focuses on dynamic run- time optimizations to enable the compiled co de schedule to flow at high throughput. this strategy increases the synergy betw een hardware and software, and leads to greater overall performance. the dual-core intel itanium processor 9000 and 9100 series provides a 6-wide and 8- stage deep pipeline, running at up to 1.6 ghz. this provides a combination of abundant resources to exploit ilp as well as increa sed frequency for minimizing the latency of each instruction. the resources consist of six integer units, six multimedia units, two load and two store units, three branch unit s, two extended-preci sion floating-point units, and one additional single-precision floating-point unit per core. the hardware employs dynamic prefetch, branch prediction, a register scoreboard, and non-blocking caches to optimize for compile-time non-de terminism. three levels of on-die cache minimize overall memory latency. this includes up to a 24 mb l3 cache, accessed at core speed, providing up to 8.53 gb/sec. of data bandwidth. the system bus is designed to support up to four physical processors (on a single system bus), and can be used as an effective building block for very large systems. the balanced core and memory subsystem provide high performance for a wide range of applications ranging from commercial workloads to high-performance technical computing. the dual-core intel itanium processor 900 0 and 9100 series supports a range of computing needs and configurations from a two-way to large smp servers. this document provides the electrical, mechanical and thermal specifications for the dual- core intel itanium processor 9000 and 91 00 series for use while employing systems with the processors. 1.2 processor abstraction layer the dual-core intel itanium processor 9000 and 9100 series requires implementation- specific processor abstraction layer (pal) firmware. pal firmware supports processor initialization, error recovery, and other functi onality. it provides a consistent interface to system firmware and operating systems across processor hardware implementations. the intel ? itanium ? architecture software developer?s manual, volume 2: system architecture, describes pal. platforms must provide access to the firmware address space and pal at reset to allow the processors to initialize.
12 dual-core intel ? itanium ? processor 9000 and 9100 series datasheet introduction the system abstraction layer (sal) firmware contains platform-specific firmware to initialize the platform, boot to an operatin g system, and provide runtime functionality. further information about sal is available in the intel ? itanium ? processor family system abstraction layer specification . 1.3 mixing processors of different frequencies and cache sizes all dual-core intel itanium processor 9000 and 9100 series on the same system bus are required to have the same cache size (24 mb, 18 mb, 12 mb, 8 mb or 6 mb) and identical core frequency. mixing components of different core frequencies and cache sizes is not supported and has not been valid ated by intel. operating system support for multiprocessing with mixed compon ents should also be considered. while intel has done nothing to specifically prevent processors within a multiprocessor environment from operating at differing fr equencies and differing cache sizes, there may be uncharacterized errata that exist in such configurations. customers would be fully responsible for validation of system co nfigurations with mixed components other than the supported configurations described above. 1.4 terminology in this document, ?the processor? refers to the ?dual-core intel itanium processor 9000 and 9100 series? processor, unless otherwise indicated. a ?#? symbol after a signal name refers to an active low signal. this means that a signal is in the active state (based on the name of the signal) when driven to a low level. for example, when reset# is low, a processo r reset has been requested. when nmi is high, a non-maskable interrupt has occurred. in the case of lines where the name does not imply an active state but describes part of a binary sequence (such as address or data), the ?#? symbol implies that the signal is inverted. for example, d[3:0] = ?hlhl? refers to a hex ?a?, and d [3:0] # = ?lhlh? also refers to a hex ?a? (h = high logic level, l = low logic level). the term ?system bus? refers to the interfac e between the processor, system core logic, and other bus agents. the system bus is a multiprocessing interface to processors, memory, and i/o. a signal name has all capitalized letters, for example, vcterm. a symbol referring to a voltage level, current level, or a time value carries a plain subscript, for example, v core , or a capitalized, abbreviated subscript, for example, t co . 1.5 state of data the data contained in this document is subj ect to change. it is the best information that intel is able to provide at the publication date of this document.
dual-core intel ? itanium ? processor 9000 and 9100 series datasheet 13 introduction 1.6 reference documents the reader of this specification should al so be familiar with material and concepts presented in the following documents: note: contact your intel representative or chec k http://developer.intel.com for the latest revision of the reference documents. intel ? itanium ? 2 processor specification update intel ? itanium ? architecture software developer?s manual, volume 1: application architecture intel ? itanium ? architecture software developer?s manual, volume 2: system architecture intel ? itanium ? architecture software developer?s manual, volume 3: instruction set reference intel ? itanium ? 2 processor reference manual for software development and optimization intel ? itanium ? processor family system abstraction layer specification itp700 debug port design guide system management bus specification
14 dual-core intel ? itanium ? processor 9000 and 9100 series datasheet introduction
dual-core intel ? itanium ? processor 9000 and 9100 series datasheet 15 electrical specifications 2 electrical specifications this chapter describes the electrical spec ifications of the dual-core intel itanium processor 9000 and 9100 series. 2.1 dual-core intel ? itanium ? processor 9000 and 9100 series system bus most dual-core intel itanium processor 9000 and 9100 series signals use the itanium processor?s assisted gunning transceiver logic (agtl+) signaling technology. the termination voltage, v cterm , is generated on the baseboard and is the system bus high reference voltage. the buffers that drive most of the system bus signals on the processor are actively driven to v cterm during a low-to-high transition to improve rise times and reduce noise. these signals should still be considered open-drain and require termination to v cterm which provides the high level. the processor system bus is terminated to v cterm at each end of the bus. there is also support of off-die termination, in which case, the termination is provided by external resistors connected to v cterm . agtl+ inputs use differential receivers which require a reference signal (v ref ). v ref is used by the receivers to determine if a signal is a logical 0 or a logical 1. the processor generates v ref on-die, thereby eliminating the need for an off-chip reference voltage source. 2.1.1 system bus power pins vcterm (1.2 v) input pins on the processor provide power to the driver buffers and on- die termination. the gnd pins, in addition to the gnd input at the power tab connector, provide ground to the processor. power for the processor core is supplied through the power tab connector by v core , v cache, v fixed. the 3.3 v pin is included on the processor to provide power to the system management bus (smbus). the v cterm , 3.3 v, and gnd pins must remain electrically separated from each other. 2.1.2 system bus no connect all pins designated as ?n/c? or ?no connect? must remain unconnected. 2.2 system bus signals 2.2.1 signal groups ta b l e 2 - 1 shows processor system bus signals that have been combined into groups by buffer type and whether they are inputs, outputs, or bidirectional, with respect to the processor.
16 dual-core intel ? itanium ? processor 9000 and 9100 series datasheet electrical specifications .. all system bus outputs should be treated as open drain signals and require a high-level source provided by the v cterm supply. agtl+ inputs have differential input buffers which use v ref as a reference level. agtl+ output signals require termination to v cterm . in this document, ?agtl+ input signals? refers to the agtl+ input group as well as the agtl+ i/o group when receiving. similarly, ?agtl+ output signals? refers to the agtl+ output group as well as the agtl+ i/o group when driving. the test access port (tap) connection input signals use a non-differential receiver with levels that are similar to agtl+. no reference voltage is required for these signals. the tap connection output signals are agtl+ output signals. the processor system bus requires terminatio n on both ends of the bus. the processor system bus supports both on-die and off-die termination controlled by two pins, terma and termb. please see the terma and termb pin description in section 2.2.2 . the hstl clock signals are the differential clock inputs for the processor. the smbus signals and lvttl power pod signals are driven using the 3.3 v cmos logic levels listed in ta b l e 2 - 8 and ta b l e 2 - 9 , respectively. table 2-1. itanium ? processor system bus signal groups group name signals agtl+ input signals bpri#, br[3:1]#, defer#, gseq#, id[9:0]#, ids#, reset# 1 , rs[2:0]#, rsp#, trdy# notes: 1. signals will not be terminated on-die even when on-die terminat ion (odt) is enabled. see the intel ? itanium ? 2 processor hardware developer?s manual for further details. agtl+ i/o signals a[49:3]#, ads#, ap[1 :0]#, berr#, binit#, bnr#, bpm[5:0]# 1 , br0#, d[127:0]#, dbsy#, dep[15:0]#, drdy#, hit#, hitm#, lock#, req[5:0]#, rp#, sbsy#, stbn[7:0]#, stbp[7:0]#, tnd# agtl+ output signals ferr#, thrmtrip#, dbsy[1:0]#, drdy[1:0]#, sbsy[1:0]# special agtl+ asynchronous interrupt input signals a20m#, ignne#, init#, lint[1,0], pmi# power good signal 1 pwrgood hstl clock signals bclkn, bclkp tap input signals 1 tck, tdi, tms, trst# tap output signals 1 tdo system management signals 1 3.3 v, sma[2:0], smsc, smsd, smwp, thrmalert# power signals gnd, vcterm lvttl power pod signals 1 cpupres#, outen, ppodgd# other terma, termb, tuner1, tuner2, tuner3, vccmon, vssmon
dual-core intel ? itanium ? processor 9000 and 9100 series datasheet 17 electrical specifications 2.2.2 signal descriptions appendix a, ?signals reference? , contains functional descriptions of all system bus signals and lvttl power pod signals. further descriptions of the system management signals are contained in chapter 6 . the signals listed under the ?power? and ?other? group are described here: v cterm system bus termination voltage. gnd system ground. n/c no connection can be made to these pins. terma, termb the processor uses two pi ns to control the on-die termination function: terma and termb. both of these termination pins must be pulled to vcterm in order to terminate the system bus using the on-die termination resist ors. both of these termination pins must be pulled to gnd in order to use off-die termination. tuner1, tuner2, tuner3 the tuner1 pin can either be left as a no-connect or left connected to vcterm via resistor for the majority of platforms supporting the dual-core intel itanium processor 9000 and 9100 series. the tuner2 resistor is used to control the termination resistance for the system bus i/o buffers. a lower resistance will cause a lower on-d ie termination resistance. on- die termination mode will only be selected if the terma and termb pins are terminated as indicated above. the tuner3 pin will not be required for the majority of platforms supporting the dual-core intel itanium processor 9000 and 9100 series. the tuner3 pin is used only in the case where a[21:17]# are driven to all zeros or all ones during the configuration cycles at reset. when all zeros or all ones are observed by the processor the presence of the tuner3 and tuner1 pins is used to determine system bus frequency. see ta b l e 2 - 2 2 for the various tuner pin combinations and resulting system bus frequency and slew rate combination. vccmon, vssmon these pins allows remote measurement of on-die vcore voltage. no connections that constitute a current load can be made to these pins. table 2-2. nominal resistance values for tuner1, tuner2, and tuner3 400 mhz 5-load platform (ohms) 400 mhz 3-load platform (ohms) 533 mhz 3-load platform (ohms) tu ne r 1 : n c 1 tuner2: 150 tu ne r 3 : n c 1 notes: 1. depending on system configuration, the processor may or may not require a resistor on the tuner pin. oems may leave the pin unconnected or connect it to vcterm through a 150 or 100 ohm resistor. if a[21:17]:# are driv en to all 0?s or all 1?s at reset, see table 2-22 for proper use of the tuner pins. tuner1: nc 1 tuner2: 150 tuner3: nc 1 tu ne r 1 : n c 1 tuner2: 150 tu ne r 3 : n c 1
18 dual-core intel ? itanium ? processor 9000 and 9100 series datasheet electrical specifications 2.3 package specifications ta b l e 2 - 3 through ta b l e 2 - 9 list the dc voltage, current , and power specifications for the processor. the voltage and current specif ications are defined at the processor pins. operational specifications listed in ta b l e 2 - 3 through ta b l e 2 - 9 are only valid while meeting specifications for case temperature, clock frequency, and input voltages. 2.4 signal specifications this section describes the dc specifications of the system bus signals. the processor signal?s dc specifications are defined at the processor pins. ta b l e 2 - 4 through ta b l e 2 - 9 describe the dc specifications for the agtl+, pwrgood, hstl clock, tap port, system management, and lvttl signals. please refer to the itp700 debug port design guide for the tap connection signals? dc specifications at the debug port. table 2-3. processor pa ckage specifications symbol parameter core frequency minimum typ maximum unit notes v core, ps v cc from the voltage regulator all vid-17 mv vid vid+17 mv v 1 notes: 1. the range for vcore is 1.0875 v to 1.25 v. v cache, ps v cache from the voltage regulator all vid-17 mv vid vid+17 mv v 2 2. vcache typical is 1.025 v. v fixed, ps v fixed from the voltage regulator all 1.25-20 mv 1.25 1.25+20 mv v v cterm termination voltage all 1.2-1.5% 1.2 1.2+1.5% v r term recommended termination resistance all 45-15% 45 45+15% ohm 3 3. the processor system bus is terminated at each end of the system bus. the processor supports both on-die and off-die termination which is selected by the term a and termb pins. termination tolerance is 15% for on-die termination measured at v ol and 1% for off-die termination. v tap test access port voltage (vcc tap ) all 1.2-1.5% 1.2 1.5 v i core,ps core current required from power supply all 2.8 89 121 a i cache,ps cache current required from power supply all 2.0 17 18 a i fixed,ps fixed current required from power supply all 0.7 9.2 11 a i cterm termination voltage current all 7.2 a 4 4. this is measured for on-die termin ation with a 45-ohm pull up resistor. ps tt power supply slew rate for the termination voltage at the processor pins all 0.05 a/ns pwr max max power all 177 w 5 5. max power is peak electrical power that must be provided for brief periods by the vr. pwr tpe thermal power envelope all 130 w pwr tdp thermal design power ? dual core all 104 w 6 6. represents the tdp level that should be used for system thermal design. sustained power for all real-world applications will remain at or below this power level. thermal design power ? single core 1.6 ghz 75 w
dual-core intel ? itanium ? processor 9000 and 9100 series datasheet 19 electrical specifications table 2-4. agtl+ signals dc specifications symbol parameter core frequency minimum typ maximum unit notes v il input low voltage all 0.625 v 1 notes: 1. the typical transition point between v il and v ih assuming 125 mv v ref uncertainty for odt. v ref_high and v ref_low levels are v ref 100 mv, respectively, for a system bu s agent using on-boa rd termination. v ref_high and v ref_low levels are v ref 125 mv, respectively, for a system bus agent using on-die termination. v ih input high voltage all 0.875 v 1 v ol output low voltage all 0.3 0.4 v 2 2. parameter measured into a 22.5 ohm resistor to 1.2 v. minimum v ol and i ol are guaranteed by design/ characterization. v oh output high voltage all v cterm , minimum v cterm v cterm , maximum v i ol output low current @ 0.3 v all 34 ma 3 3. calculated using off-die termination thro ugh two 45 ohm 1% resistors in parallel. i ol output low current @ 0.3 v all 17 ma 4 4. calculated using on-die termination to a 45 15% resistor measured at v ol . i l leakage current all 100 a 5 5. at 1.2 v 1.5%. v cterm , minimum vpin v cterm , maximum. c agtl+ agtl+ pad capacitance all 2 pf 6 6. total of i/o buffer with esd structure and processor pa rasitics if applicable. capacitance values guaranteed by design for all agtl+ buffers. table 2-5. power good si gnal dc specifications symbol parameter minimum maximum unit notes v il input low voltage 0.440 v v ih input high voltage 0.875 v table 2-6. system bus clock differential hstl dc specifications symbol parameter minimum maximum unit notes v ih input high voltage 0.78 1.3 v v il input low voltage ?0.3 0.5 v v x input crossover voltage 0.55 0.85 v c clk input (pad) capacitance 1.75 pf table 2-7. tap connection dc specifications symbol parameter minimum maximum unit notes v il input low voltage ?0.3 0.5 v 1 notes: 1. there is a 100 mv hysteresis on tck. v ih input high voltage 1.1 1.57 v 1, 2 2. v ih, max = 1.5 v + 5%, v oh, max = 1.2 v +5%. v ol output low voltage 0.3 v v oh output high voltage 1.2 v 2, 3 3. there is no internal pull-up. an exte rnal pull-up is always assumed. max voltage tolerated at tdo is 1.5 v. i ol output low current 20 ma i ic input current 690 ua 4 4. per input pin.
20 dual-core intel ? itanium ? processor 9000 and 9100 series datasheet electrical specifications ta b l e 2 - 1 0 through ta b l e 2 - 1 1 list the ac specifications for the processor?s clock and smbus (timing diagrams begin with figure 2-1 ). the processor uses a differential hstl clocking scheme with a frequency of 200, 266, or 333 mhz. the smbus is a subset of the i2c* interface which supports operation of up to 100 khz. table 2-8. smbus dc specifications symbol parameter minimum typ maximum unit notes 3.3v v cc for the system management components 3.14 3.3 3.47 v 3.3 v 5 v il input low voltage ?0.3 0.3*3.3 v v v ih input high voltage 2.31 3.47 v max = 3.3 +5% min + 0.7*3.3v v ol output low voltage 0.4 v i 3.3v 3.3v supply current 5.0 30.0 ma i ol output low current 3 ma 1 notes: 1. the value specified for i ol applies to all signals except for thrmalert#. i ol2 output low current 6 ma 2 2. the value specified for i ol2 applies only to thrmalert#, which is an open drain signal. i li input leakage current 10 a i lo output leakage current 10 a table 2-9. lvttl signal dc specifications symbol parameter minimum maximum unit notes v il input low voltage 0.8 v v ih input high voltage 2.0 3.63 v v ol output low voltage 0.4 v v oh output high voltage 2.4 v table 2-10.system bus clock differential hstl ac specifications (sheet 1 of 2) symbol parameter system bus clock (mhz) minimum typ maximum unit figure notes t period bclkp period 200 5.0 ns figure 2-1 t skew system clock skew 200 100 ps 1 f bclk bclkp frequency 200 200 200 mhz figure 2-1 2 t jitter bclkp input jitter 200 100 ps figure 2-1 3 t high bclkp high time 200 2.25 2.5 2.75 ns figure 2-1 4 t low bclkp low time 200 2.25 2.5 2.75 ns figure 2-1 4 t period bclkp period 266 3.75 ns figure 2-1 t skew system clock skew 266 60 ps 5 f bclk bclkp frequency 266 266 266 mhz figure 2-1 2 t jitter bclkp input jitter 266 50 ps figure 2-1 3 t high bclkp high time 266 1.69 1.88 2.06 ns figure 2-1 4 t low bclkp low time 266 1.69 1.88 2.06 ns figure 2-1 4
dual-core intel ? itanium ? processor 9000 and 9100 series datasheet 21 electrical specifications t rise bclkp rise time 7 all 333 500 667 ps figure 2-1 20?80% t fall bclkp fall time 7 all 333 500 667 ps figure 2-1 20?80% v pp minimum input swing all 600 mv figure 2-1 6 notes: 1. the system clock skew is 100 ps. 2. measured on cross-point of ri sing edge of bclkp and falling ed ge of bclkn. long-ter m jitter is defined as peak-to-peak variat ion measured by accumulating a large number of cl ock cycles and recording peak-to-peak jitter. 3. cycle-to-cycle jitter is defined as peak-to-peak vari ation measured over 10,000 cycles peak-to-peak jitter. 4. measured on cross point of rising edge of bclkp and falling edge of bclkn. 5. the system clock skew is 60 ps. 6. v ppmin is defined as the minimum input diffe rential voltage which will cause no incr ease in the clock receiver timing. 7. the measurement is taken at 40-60% of the signal and extrapolated to 20-80%. table 2-11. smbus ac specifications symbol parameter minimum maximum unit notes f smsc smsc clock frequency 100 khz t smsc smsc clock period 10 s t high smsc clock high time 4.0 s 1 notes: 1. please refer to figure 2-2 for the standard microsystems corporation (smsc)* clock waveform. t low smsc clock low time 4.7 s 1 t rise smsc clock rise time 1.0 s 1 t fall smsc clock fall time 0.3 s 1 t valid smbus output valid delay 1.0 s t su smbus input setup time 250 ns t hld smbus input hold time 0 ns t free bus free time 4.7 s 2 2. bus free time is the minimum time allowed between request cycles. figure 2-1. generic clock waveform 000615 table 2-10.system bus clock differential hstl ac specifications (sheet 2 of 2) symbol parameter system bus clock (mhz) minimum typ maximum unit figure notes 80% t rise t rise rise time t fall fall time high time t high low time t low = = = = 20% t fall t high t low t period t jitter bclkn bclkp v pp = t period period t jitter long term peak-to-peak jitter peak-to-peak swing = = = v pp
22 dual-core intel ? itanium ? processor 9000 and 9100 series datasheet electrical specifications 2.4.1 maximum ratings ta b l e 2 - 1 2 contains the processor stress ratings. functional operation at the absolute maximum and minimum is neither implied nor guaranteed. the processor should not receive a clock while subjected to these conditions. functional operating conditions are given in the dc tables. extended exposure to the maximum ratings may affect device reliability. furthermore, although the processor contains protective circuitry to resist damage from static electric discharge, one should always take precautions to avoid static voltages or electric fields. figure 2-2. smsc clock waveform 000618 smsc t rise t high t fall t low t rise rise time t fall fall time = = t high high time t low low time = = 90% v cc v (3.3v) cc 75% v cc 25% v cc table 2-12. dual-core intel ? itanium ? processor absolute maximum ratings symbol parameter minimum maximum unit notes t storage processor storage temperature ?10 45 c 1 notes: 1. storage temperature is temperature in which the processor can be stored for up to one year. t shipping processor shipping temperature ?45 75 c 2 2. shipping temperature is temperature in which the processor can be shipped for up to 24 hours. v core any v core voltage with respect to gnd -0.3 1.55 v v cache any v cache voltage with respect to gnd -0.3 1.55 v v fixed any v fixed voltage with respect to gnd -0.3 1.55 v 3.3v any 3.3 v supply vo ltage with respect to gnd ?0.3 5.5 v 3 3. parameters are from third-party vendor specifications. v in, smbus smbus buffer dc input voltage with respect to gnd ?0.1 6.0 v 3 v in, agtl+ agtl+ buffer dc input voltage with respect to gnd ?0.45 1.65 v 4, 5 4. maximum instantaneous voltag e at receiver buffer input. 5. specification includes v in,agtl+ and v in,agtl+ asynchronous (agtl+ asynchronous buffer dc input voltage with respect to gnd. v cterm any v cterm voltage with respect to gnd -0.45 1.65 v v in,tap tap buffer dc input voltage with respect to gnd. -0.45 1.65 v 4
dual-core intel ? itanium ? processor 9000 and 9100 series datasheet 23 electrical specifications 2.5 system bus signal quality specifications and measurement guidelines overshoot (or undershoot) is the absolute value of the maximum voltage above the nominal v cterm voltage (or below gnd), as shown in ta b l e 2 - 3 . the overshoot/ undershoot specifications limit transitions beyond v cterm or gnd due to the fast signal edge rates. the processor can be permanently damaged by repeated overshoot or undershoot events on any input, output, or i/o buffer if the charge is large enough (that is, if the overshoot/undershoot is grea t enough). determining the impact of an overshoot/undershoot condition requires knowledge of the magnitude, the pulse duration, and the activity factor (af). 2.5.1 overshoot/undershoot magnitude magnitude describes the maximum potential difference between a signal and its voltage reference level. for the processor, both are referenced to gnd, as shown in figure 2-3 . it is important to note that overshoot and undershoot conditions are separate and their impact must be determined independentl y. overshoot/undershoot magnitude levels must observe the absolute maximum specifications listed in ta b l e 2 - 1 3 through ta b l e 2 - 1 7 . these specifications must not be violated at any time, regardless of bus activity or system state. within these specifications are threshold levels that define different allowed pulse duration. provided that the magnitude of the overshoot/ undershoot is within the absolute maxi mum specifications, the pulse magnitude, duration, and activity factors must all be used to determine if the overshoot/ undershoot pulse is within specifications. figure 2-3. system bus signal wavefo rm exhibiting overshoot/undershoot 000588 v cterm maximum absolute overshoot maximum absolute undershoot time-de p endent overshoot time-de p endent undershoot v ref v ol gnd v min v max
24 dual-core intel ? itanium ? processor 9000 and 9100 series datasheet electrical specifications 2.5.2 overshoot/undershoot pulse duration pulse duration describes the total time that an overshoot/undershoot event exceeds the overshoot/undershoot reference voltage (v cterm /gnd). the total time could encompass several oscillations above the reference voltage. multiple overshoot/ undershoot pulses within a single over shoot/undershoot event may need to be measured to determine the total pulse duration. note: oscillations below the reference voltage cannot be subtracted from the total overshoot/ undershoot pulse duration. 2.5.3 activity factor activity factor (af) describes the freque ncy of overshoot (or undershoot) occurrence relative to a clock. since the highest frequency of assertion of any common clock signal is every other clock, an af = 1 indicates that the specific overshoot (or undershoot) waveform occurs every other clock cycle. thus, an af = 0.01 indicates that the specific overshoot (or undershoot) waveform occurs one time in every 200 clock cycles. for source synchronous signals (data, and associated strobes), the activity factor is in reference to the strobe edge. the highest frequency of assertion of any source synchronous signal is every active edge of its associated strobe. so, an af = 1 indicates that the specific overshoot (or undershoot) waveform occurs every other strobe cycle. the specifications provided in ta b l e 2 - 1 4 through ta b l e 2 - 1 7 show the maximum pulse duration allowed for a gi ven overshoot/undershoot magnitude at a specific activity factor. each table entry is independent of all others, meaning that the pulse duration reflects the existence of ov ershoot/undershoot events of that magnitude only. a platform with an overshoot/undershoot that just meets the pulse duration for a specific magnitude where the af <1, means that there can be no other overshoot/ undershoot events, even of lesser magnitude (if af = 1, then the event occurs at all times and no other events can occur). note: af for the common clock agtl+ signals is referenced to bclkn, and bclkp frequency. the wired-or signals (binit#, hit#, hitm#, bnr#, tnd#, berr#) are common clock agtl+ signals. note: af for source synchronous (2x) signals is referenced to stbp#[7:0], and stbn#[7:0]. 2.5.4 reading overshoot/unde rshoot specif ication tables the overshoot/undershoot specification for the processor is not a simple single value. instead, many factors are needed in order to correctly interpret the overshoot/ undershoot specification. in addition to the magnitude of the overshoot, the following parameters must also be known: the width of the overshoot and the af. to determine the allowed overshoot for a particular overshoot event, the following must be done: 1. determine the signal group that the particular signal falls into. for agtl+ signals operating in the 2x source synchronous domain, use ta b l e 2 - 1 4 through ta b l e 2 - 1 6 . if the signal is a wired-or agtl+ signal operating in the common clock domain, use ta b l e 2 - 1 5 through ta b l e 2 - 1 7 . 2. determine the magnitude of the overshoot, or the undershoot (relative to gnd). 3. determine the activity factor (how often does this overshoot occur?). 4. next, from the appropriate spec ification table, determine the maximum pulse duration (in nanoseconds) allowed. the pulse duration shown in the table refers to the period where either the maximum over shoot (for high phase) and undershoot (for low phase) occurred.
dual-core intel ? itanium ? processor 9000 and 9100 series datasheet 25 electrical specifications 5. compare the specified maximum pulse dura tion to the signal being measured. if the pulse duration measured is less than the pulse duration shown in the table, then the signal meets the specifications. 6. undershoot events must be analyzed sepa rately from overshoot events, as they are mutually exclusive. 2.5.5 determining if a system meets the overshoot/undershoot specifications the overshoot/undershoot specifications listed in ta b l e 2 - 1 3 through ta b l e 2 - 1 7 specify the allowable overshoot/undershoot for a single overshoot/undershoot event. however, most systems will have multiple overshoot and/or undershoot events that each has their own set of parameters (duration, af and magnitude). while each overshoot on its own may meet the overshoot specification, the total impact of all overshoot events may cause the system to fail. a guideline to ensure a system passes the overshoot and undershoot specifications is shown below: 1. ensure that no signal ever exceeds v cterm or gnd. 2. if only one overshoot/undershoot event ma gnitude occurs, ensure that it meets the specifications listed in ta b l e 2 - 1 3 through ta b l e 2 - 1 7 . 3. if multiple overshoots and/or multiple undershoots occur, measure the worst-case pulse duration for each magnitude and compare the results against the af = 1 specifications. if all of these worst-case overshoot or undershoot events meet the specifications (measured time < specificat ions) in the table (where af = 1), then the system passes. 2.5.6 wired-or signals to ensure platform compatibility between the processors, system bus signals must meet certain overshoot and undershoot requirements. the system bus wired-or signals (binit#, hit#, hitm#, bnr#, tnd#, berr#) have the same absolute overshoot and undershoot specification as the source synchronous agtl+ signals, but they have different time-dependent overshoot/undershoot requirements. notes: the following notes apply to ta b l e 2 - 1 4 through ta b l e 2 - 1 7 : 1. absolute maximum overshoot magnitude of 1.65 v must never be exceeded. 2. absolute maximum overshoot is meas ured referenced to gnd. pulse duration of overshoot is measured relative to v cterm . 3. absolute maximum undershoot and pulse duration of undershoot is measured relative to gnd. 4. ringback below v cterm cannot be subtracted from overshoots/undershoots. 5. lesser undershoot does not allocate overshoot with longer duration or greater magnitude. 6. all values specified by design characterization. table 2-13. source synchronous agtl+ signal group and wired-or signal group absolute overshoot/undershoot tolerance parameter description specification units v cterm i/o power supply voltage (nominal). 1.20 v v max maximum absolute voltage for system bus signals at the input of the receiver buffers. 1.65 v v min minimum absolute voltage for system bus signals at the input of the receiver buffers. ?0.45 v overshoot time dependent overshoot amount above v cterm . 1 notes: 1. these parameters cannot be specified in absolute terms. undershoot time dependent undershoot amount below gnd. 1
26 dual-core intel ? itanium ? processor 9000 and 9100 series datasheet electrical specifications table 2-14. source synchronous agtl+ si gnal group time-dependent overshoot/ undershoot tolerance for 400-mhz system bus absolute maximum (v) pulse duration (ns) over- shoot under- shoot af = 1 1 notes: 1. activity factor = 1 means signal toggles every 5 ns. af = 0.75 af = 0.5 af = 0.25 af = 0.1 af = 0.05 af = 0.01 1.65 ?0.45 0.0035 0.0036 0.0037 0.0040 0.0121 0.0241 0.1207 1.6 ?0.4 0.0039 0.0040 0.0045 0.0157 0.0396 0.0799 0.3996 1.55 ?0.35 0.0124 0.0168 0.0255 0.0520 0.1309 0.2626 1.3107 1.5 ?0.3 0.0405 0.0546 0.0833 0.1682 0.4279 0.8546 2.5 1.45 ?0.25 0.1304 0.1755 0.2671 0.5438 1.3629 2.5 2.5 1.4 ?0.2 0.4136 0.5581 0.8524 1.7215 2.5 2.5 2.5 1.35 ?0.15 1.3163 1.7815 2.5 2.5 2.5 2.5 2.5 1.3 ?0.1 2.5 2.5 2.5 2.5 2.5 2.5 2.5 1.25 ?0.05 2.5 2.5 2.5 2.5 2.5 2.5 2.5 table 2-15. wired-or signal group (bin it#, hit#, hitm#, bnr#, tnd#, berr#) overshoot/undershoot toleranc e for 400-mhz system bus absolute maximum (v) pulse duration (ns) over- shoot under- shoot af = 1 1 notes: 1. activity factor = 1 means signal toggles every 10 ns. af = 0.75 af = 0.5 af = 0.25 af = 0.1 af = 0.05 af = 0.01 1.65 ?0.45 0.0166 0.0192 0.0306 0.0614 0.1539 0.3067 1.5374 1.6 ?0.4 0.0506 0.0674 0.1017 0.2032 0.5090 1.0213 5 1.55 ?0.35 0.1659 0.2216 0.3342 0.6676 1.6734 3.3413 5 1.5 ?0.3 0.5413 0.7218 1.0840 2.1814 5 5 5 1.45 ?0.25 1.7343 2.3194 3.4995 5 5 5 5 1.4?0.25555555 1.35?0.155555555 table 2-16. source synchronous agtl+ si gnal group time-dependent overshoot/ undershoot tolerance for 533-mhz system bus (sheet 1 of 2) absolute maximum (v) pulse duration (ns) over- shoot under- shoot af = 1 1 af = 0.75 af = 0.5 af = 0.25 af = 0.1 af = 0.05 af = 0.01 1.65 ?0.45 0.0026 0.0027 0.0028 0.0030 0.0091 0.0181 0.0902 1.6 ?0.4 0.0029 0.0030 0.0034 0.0118 0.0297 0.0600 0.2989 1.55 ?0.35 0.0093 0.0126 0.0191 0.0387 0.0980 0.1963 0.9822 1.5 ?0.3 0.0303 0.0409 0.0625 0.1268 0.3178 0.6406 1.875 1.45 ?0.25 0.3095 0.4191 0.6366 1.2965 1.875 1.875 1.875
dual-core intel ? itanium ? processor 9000 and 9100 series datasheet 27 electrical specifications 2.6 voltage regulator connector signals the vr module consists of three dc-dc converters, v core , v cache , and v fixed . ta b l e 2 - 1 8 lists all of the signals which are part of the processor package vr output connector. warning: if the vr cannot supply the voltages requ ested by the components in the processor package, then it must disable itself. figure 2-4 shows the top view of the processor package power tab. see ta b l e 2 - 1 9 for power tab connector signals. 1.4 ?0.2 0.9925 1.3358 1.875 1.875 1.875 1.875 1.875 1.35 ?0.15 1.875 1.875 1.875 1.875 1.875 1.875 1.875 1.3 ?0.10 1.875 1.875 1.875 1.875 1.875 1.875 1.875 notes: 1. activity factor = 1 means signal toggles every 3.75 ns. table 2-17. wired-or signal group (binit#, hit#, hitm#, bnr#, tnd#, berr#) overshoot/undershoot tolera nce for 533-mhz system bus absolute maximum (v) pulse duration (ns) over- shoot under- shoot af = 1 1 notes: 1. activity factor = 1 means signal toggles every 7.5 ns. af = 0.75 af = 0.5 af = 0.25 af = 0.1 af = 0.05 af = 0.01 1.65 ?0.45 0.01248 0.0144 0.0230 0.0461 0.1155 0.2301 1.1530 1.6 ?0.4 0.0380 0.0507 0.0763 0.1522 0.3814 0.7627 3.75 1.55 -0.35 0.1250 0.1668 0.2507 0.5004 1.2537 2.5059 3.75 1.5 ?0.3 0.4054 0.5424 0.8163 1.6302 3.75 3.75 3.75 1.45 ?0.25 1.3013 1.7396 2.6246 3.75 3.75 3.75 3.75 1.4 -0.2 3.75 3.75 3.75 3.75 3.75 3.75 3.75 1.35 ?0.15 3.75 3.75 3.75 3.75 3.75 3.75 3.75 table 2-16. source synchronous agtl+ si gnal group time-dependent overshoot/ undershoot tolerance for 533- mhz system bus (sheet 2 of 2) absolute maximum (v) pulse duration (ns) table 2-18. vr connector signals group name signals voltage regulator connector ppodgd#, cpupres#, gnd, vid_valid, vid_core[5:0], vid_cache [5:0], vcache_sense, gnd_sense, vcore_sense, vfixed_sense, outen.
28 dual-core intel ? itanium ? processor 9000 and 9100 series datasheet electrical specifications figure 2-4. processors power tab physical layout 001356 table 2-19. power connector pinouts (sheet 1 of 2) power tab vr pads description a1 - c1 gnd l1 - n1 gnd a2 ppodgd# b2 cpupres# d1, k1, c2, d2, e2 vfixed h2 - n2 vfixed a3 vid_valid b3 vid_core [0] c3 vid_core [1] d3 vid_core [2] e3 vid_core [3] f3 vid_core [4] g3 vid_core [5] h3 vid_cache [0] j3 vid_cache [1] k3 vid_cache [2] l3 vid_cache [3] m3 vid_cache [4] n3 vid_cache [5] a4 - n4 gnd a5 - n5 vcache a6 - n6 gnd a7 - n7 vcore a8 - n8 gnd a9 - n9 vcore
dual-core intel ? itanium ? processor 9000 and 9100 series datasheet 29 electrical specifications the vr shall provide a selectable output volt age controlled via multiple binary weighted voltage identification (vid) inputs. the vid value (high = 1; low = 0) is defined in ta b l e 2 - 2 0 . vid pins will be controlled by the processor. a10 - n10 gnd a11 - n11 vcore a12 - n12 gnd a13 - n13 vcore a14 - n14 gnd a15 - n15 vcore a16 - n16 gnd a17 - n17 vcore a18 - n18 gnd a19 - n19 vcore a20 - n20 gnd a21 - n21 vcore a22 - n22 gnd a23 - n23 vcore a24 - n24 gnd a25 - n25 vcore a26 - n26 gnd a27 - n27 vcache a28 - n28 gnd a29 vcache_sense b29 gnd_sense c29 vcore_sense d29 vfixed_sense k29 gnd l29 reserved m29 reserved n29 outen a30 - d30 gnd l30 - n30 gnd table 2-19. power connector pinouts (sheet 2 of 2) power tab vr pads description
30 dual-core intel ? itanium ? processor 9000 and 9100 series datasheet electrical specifications table 2-20. processors core voltage identification code (v core and v cache) processor pins (0 = low, 1 = high) 400 200 100 50 25 12.5 (mv) 400 200 100 50 25 12.5 (mv) vid 5 vid 4 vid 3 vid 2 vid 1 vid 0 vout (v) vid 5 vid 4 vid 3 vid 2 vid 1 vid 0 vout (v) 111111 off011111 0. 9125 111110 1.3011110 0.9 111101 1. 2875 0 1 1101 0. 8875 111100 1.275011100 0.875 111011 1. 2625 0 1 1011 0. 8625 111010 1.25011010 0.85 111001 1. 2375 0 1 1001 0. 8375 111000 1.225011000 0.825 110111 1. 2125 0 1 0111 0. 8125 110110 1.2010110 0.8 110101 1. 1875 0 1 0101 0. 7875 110100 1.175010100 0.775 110011 1. 1625 0 1 0011 0. 7625 110010 1.15010010 0.75 110001 1. 1375 0 1 0001 0. 7375 110000 1.125010000 0.725 101111 1. 1125 0 0 1111 0. 7125 101110 1.1001110 0.7 101101 1. 0875 0 0 1101 0. 6875 101100 1.075001100 0.675 101011 1. 0625 0 0 1011 0. 6625 101010 1.05001010 0.65 101001 1. 0375 0 0 1001 0. 6375 101000 1.025001000 0.625 100111 1. 0125 0 0 0111 0. 6125 100110 1 000110 0.6 100101 0. 9875 0 0 0101 0. 5875 100100 0.975000100 0.575 100011 0. 9625 0 0 0011 0. 5625 100010 0.95000010 0.55 100001 0. 9375 0 0 0001 0. 5375 100000 0.925000000 0.525
dual-core intel ? itanium ? processor 9000 and 9100 series datasheet 31 electrical specifications 2.7 system bus clock and processor clocking the bclkn and bclkp inputs control the oper ating frequency of the processor system bus interface. all processor system bus timing parameters are specified with respect to the falling edge of bclkn and rising edge of bclkp. the address pins a[21:17]# will be used to specify the system bus frequency du ring reset. the processor will ensure that the correct bus/core ratio is elected based on the bus frequency that is specified during reset. cold reset sequence: ? the configuration pins (a[21:17]#) must be asserted the entire time reset# is asserted. ? reset# must be asserted be fore pwrgood is asserted. ? the duration from the assertion of pwrgood to the deassertion of reset# must be 1 millisecond minimum. ? after reset# is deasserted, all the config uration, including pins a[21:17]#, must remain valid for 2 bclks (min imum) to 3 bclks (maximum). ? bclk is shown as a time reference to the bclk period. it is not a requirement that this is bclkn or bclkp signal. ? configuration signals other than a[21:17]# must be asserted 4 bclks prior to the deasserted edge of reset# and must re main valid for 2 bclks (minimum) to 3 bclks (maximum) after the de asserted edge of reset#. figure 2-5 outlines the timing relationship between the configuration pins, reset# and pwrgood for cold reset. figure 2-5. system bus reset and co nfiguration timings for cold reset 000859b bclk pwrgood reset# bus ratio (a[21:17]#) t a = 1.15 ns minimum; (set up time to bclk for deassertion edge of reset#) t b = 1 ms minimum for cold reset t d = 2 bclks minimum, 3 bclks maximum t e = 4 bclks minimum t f = 2 bclks minimum, 3 bclks maximum additional configuration signals t b t d t e t f t a t 1 t 2 t 3 t c t c = bus ratio signals must be asserted no later than reset# t -2 t -1 t 0 t -4 t -3
32 dual-core intel ? itanium ? processor 9000 and 9100 series datasheet electrical specifications warm reset sequence : ? pwrgood remains high throughout the entire sequence, as power is already available and stable to the processor. ? the configuration pins (a[21:17]#) must be asserted the entire time reset# is asserted. ? the duration from the assertion of reset# to the deassertion of reset# must be 1 millisecond minimum. ? after reset# is deasserted, the config uration pins must remain valid for two bclks (minimum) to three bclks (maximum). ? bclk is shown as a time reference to the bclk period. it is not a requirement that this is bclkn or bclkp signal. ? configuration signals other than a[21:17]# must be asserted four bclks prior to the deasserted edge of reset# and must remain valid for two bclks (minimum) to three bclks (maximum) after the deasserted edge of reset#. figure 2-6 outlines the timing relationship betw een the configuration pins, reset# and pwrgood for warm reset. figure 2-6. system bus reset and co nfiguration timings for warm reset 000777b bclk pwrgood reset# bus ratio (a[21:17]#) t a = 1.15 ns minimum; (set up time to bclk for deassertion edge of reset#) t b = 1 ms minimum for warm reset t d = 2 bclks minimum, 3 bclks maximum t e = 4 bclks minimum t f = 2 bclks minimum, 3 bclks maximum additional configuration signals t b t d t e t f t a t 1 t 2 t 3 t c t c = bus ratio signals must be asserted no later than reset# t -2 t -1 t 0 t -4 t -3
dual-core intel ? itanium ? processor 9000 and 9100 series datasheet 33 electrical specifications 2.8 recommended connections for unused pins pins that are unused in an application environment (as opposed to testing environment) should be connected to the states listed in ta b l e 2 - 2 1 . pins that must be used in an application are stated as such and do not have a recommended state for unused connection. table 2-21. connection for unused pins pins/pin groups recommended connections notes agtl+ pins h 1, 2 notes: 1. l = gnd, h = v cterm . 2. agtl+ output signals sbsy[0:1]#, dbsy[0:1]#, and drdy[0,1]# may be left as n/c if not used on platform. hstl clock signals must be used all power signals must be used pwrgood must be used tap signals tck l 1, 3 trst# l 1, 3 3. can be no-connect or connected to v cterm via a 100ohm or 150 ohm resistor. tdi h 1, 3 tdo h 1, 3 tms h 1, 3 system management signals 3.3v gnd sma[2:0] n/c smsc n/c smsd n/c smwp n/c thrmalert# h 1, 4 4. thrmalert# should be pulled up to 3.3 v through a resistor. lvttl power pod signals outen must be used ppodgd# must be used procpres# must be used other pins n/c n/c a20m# n/c ignne# n/c lock# n/c ferr# n/c tuner1 n/c or h 3,5 5. with a[21;17] settings to all 0? or all 1?s, please refer to table 2-22 for proper connection. tuner2 h 1 tuner3 n/c or h 3,5
34 dual-core intel ? itanium ? processor 9000 and 9100 series datasheet electrical specifications table 2-22. tuner1/tuner3 translation table a[21:17}# 1 notes: 1. 0 = v cterm , 1 = gnd tuner1 2 2. 0 = resistor not present, 1 = resistor present tuner3 2 system bus (mhz) slew rate (v/ns) 0 0 0 667 1.7 0 0 1 533 1.4 0 1 n/a 400 0.8 1 0 0 667 1.92 1 0 1 533 1.7 1 1 n/a 400 0.82
dual-core intel ? itanium ? processor 9000 and 9100 series datasheet 35 pinout specifications 3 pinout specifications this chapter describes the dual-core inte l itanium processor 9000 and 9100 series signals and pinout. note: the pins labeled ?n/c? must remain unc onnected. the processor uses a jedec standard pin naming convention. in this chapter, pin names are the actual names given to each physical pin of the processor. system bus signal names are th e names associated with the functions of those pins. for those pins associated with multiple functions, their pin names and system bus signal names are not necessarily identical. figure 3-1 shows the processor pin location diagram from the top view. figure 3-1. dual-core intel ? itanium ? processor 9000 and 9100 series pinout 000638b gnd gnd gnd gnd gnd gnd vc term gnd gnd vc term gnd vc term gnd gnd vc term gnd gnd gnd gnd id0# gnd id1# gnd a07# a06# a04# vc term d30# gnd d27# vc term d20# gnd nc vc term d11# gnd d07# vc term d04# gnd 3.3v vc term tuner[ 2] gnd gnd gnd gnd a05# d25# gnd d23# gnd d17# gnd d13# gnd d14# gnd d01# gnd nc gnd gnd id4# id5# a13# a12# gnd dep3# vc term d24# gnd stbp1# vc term d16# gnd d12# vc term stbn0# gnd d03# vc term nc nc id7# a11# gnd gnd gnd gnd d19# gnd dep1# gnd d08# gnd stbp0# gnd d02# gnd gnd rsp# id8# id9# a08# a03# vc term dep2# d26# vc term d28# d21# d18# vc term d09# d15# d06# vc term d05# gnd nc vc term ids# gnd drdy0# gnd gnd a09# gnd d31# gnd d22# gnd gnd dep0# gnd gnd d10# gnd d00# gnd thrm alert# init# rs1# gnd rs2# a17# a15# dep6# vc term d54# d48# vc term d49# gnd d42# vc term d45# gnd d37# vc term nc gnd gnd gnd gnd gnd gnd gnd gnd d53# dep4# d38# d40# gnd d35# gnd vssmon req1# req2# dbsy# hit# a24# a20# vc term dep7# d63# d61# vc term stbp3# d50# vc term d32# stbn2# vc term d34# gnd gnd vcterm req3# gnd drdy# gnd a23# gnd gnd nc gnd d60# gnd stbn3# gnd d56# gnd dep5# gnd d41# gnd stbp2# gnd d33# gnd vccmon req4# gnd req5# rp# hi tm# a25# a19# d62# vc term d57# d51# vc term nc gnd d46# vc term d44# gnd d36# vc term gnd gnd gnd gnd gnd gnd gnd d52# d47# d43# d39# gnd nc gnd gnd trdy# lock# gseq# defer# a34# a31# vc term d94# d59# d87# vc term d84# nc vc term d75# d68# vc term d65# gnd nc vc term gnd gnd tnd# gnd binit# gnd gnd a28# gnd d92# gnd d91# gnd d81# gnd d78# gnd d71# gnd d67# gnd nc gnd sma2 breq0# breq1# nc nc a36# a38# dep11# vc term d93# stbp5# vc term d83# gnd d76# vc term stbn4# gnd d66# vc term nc gnd gnd gnd gnd gnd gnd gnd gnd d88# dep9# d72# stbp4# gnd d73# gnd sma1 breq3# nc nc breq2# a35# a29# vc term dep10# d89# d95# vc term d86# d80# vc term d77# d69# vc term d64# gnd sma0 vc term bpri# gnd sbsy1# gnd gnd gnd gnd d85# gnd d82# gnd dep8# gnd d79# gnd d74# gnd d70# gnd gnd ppod gd# gnd reset# nc ads# gnd a39# a45# gnd dep14# vc term d122# gnd d118# vc term d117# gnd d111# vc term d106# gnd d102# vc term nc gnd gnd gnd gnd gnd gnd gnd d112# dep12# d101# d96# gnd d99# gnd smwp lint0 trst# bpm0# berr# a49# a47# vc term dep15# d124# d125# vc term stbp7# d114# vc term d105# stbn6# vc term d98# gnd smsd bpm2# gnd bpm3# gnd ap1# gnd gnd a42# gnd d126# gnd stbn7# gnd d116# gnd dep13# gnd d108# gnd stbp6# gnd d97# gnd gnd lint1 gnd bpm4# gnd bpm5# gnd a43# a40# gnd d123# vc term d120# gnd d115# vc term nc gnd d109# vc term d103# gnd d104# vc term smsc gnd pmi# bpm1# ap0# gnd vc term d121# d119# gnd d113# gnd d110# gnd d107# gnd d100# gnd nc gnd vc term ah ag af ae ad ac ab aa y w v u t r p n m l k j h g f e d c b a 1 2 3 4 5 6 7 8 9 1 0 11 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 21 2 2 2 3 2 4 2 5 ah ag af ae ad ac ab aa y w v u t r p n m l k j h g f e d c b a 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 power pod gnd vc term gnd a27# gnd d90# dbsy1# drdy1# a33# sbsy0# dsby0# id3# gnd gnd id2# gnd gnd gnd gnd gnd termb id6# rs0# req0# sbsy# terma gnd gnd outen gnd tuner[1] nc tdo tms nc bclkn pwr good nc nc nc a20m# ferr# gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd nc tdi tck nc bclkp proc pres# nc nc nc ignne# th_trip# gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd stbn1# d58# d55# stbn5# d127# gnd d29# gnd gnd nc a18# a16# bnr# a48# a10# a14# a21# a26# a22# a37# a32# a30# a44# a46# a41# gnd gnd
36 dual-core intel ? itanium ? processor 9000 and 9100 series datasheet pinout specifications ta b l e 3 - 1 provides the dual-core intel itanium processor 9000 and 9100 series pin list in alphabetical order. ta b l e 3 - 2 provides the dual-core intel itanium processor 9000 and 9100 series pin list by pin location. table 3-1. pin/signal information sorted by pin name (sheet 1 of 15) pin name system bus signal name pin location input/output notes 3.3v b02 in smbus supply voltage a003# aa03#/exf0# v06 in/out a004# aa04#/exf1# v02 in/out a005# aa05#/exf2# u03 in/out a006# aa06#/exf3# w03 in/out a007# aa07#/exf4# y02 in/out a008# aa08#/be0# y06 in/out a009# aa09#/be1# u07 in/out a010# aa10#/be2# v04 in/out a011# aa11#/be3# aa05 in/out a012# aa12#/be4# w05 in/out a013# aa13#/be5# y04 in/out a014# aa14#/be6# w07 in/out a015# aa15#/be7# v08 in/out a016# aa16#/did0# u13 in/out a017# aa17#/did1# y08 in/out a018# aa18#/did2# u09 in/out a019# aa19#/did3# v12 in/out a020# aa20#/did4# v10 in/out a021# aa21#/did5# w09 in/out a022# aa22#/did6# w13 in/out a023# aa23#/did7# aa11 in/out a024# aa24#/did8# y10 in/out a025# aa25#/did9# y12 in/out a026# aa26#/ab26# w11 in/out a027# aa27#/xtprvalue0# u19 in/out a028# aa28#/xtprvalue1# u15 in/out a029# aa29#/xtprvalue2# v18 in/out a030# aa30#/xtprvalue3# w19 in/out a031# aa31#/xtprdisable# v14 in/out a032# aa32#/attr0# w17 in/out a033# aa33#/attr1# aa17 in/out a034# aa34#/attr2# y14 in/out a035# aa35#/attr3# y18 in/out a036# aa36#/ab36# y16 in/out a037# aa37#/ab37# w15 in/out a038# aa38#/ab38# v16 in/out a039# aa39#/ab39# y20 in/out a040# aa40#/ab40# v24 in/out
dual-core intel ? itanium ? processor 9000 and 9100 series datasheet 37 pinout specifications a041# aa41#/ab41# w25 in/out a042# aa42#/ab42# u23 in/out a043# aa43#/ab43# y24 in/out a044# aa44#/ab44# w21 in/out a045# aa45#/ab45# v20 in/out a046# aa46#/ab46# w23 in/out a047# aa47#/ab47# v22 in/out a048# aa48#/ab48# u21 in/out a049# aa49#/ab49# y22 in/out a20m# a20m# ah23 n/c ads# ads# ab20 in/out ap0# ap0# aa25 in/out ap1# ap1# aa23 in/out bclkn bclkn ah13 in bclkp bclk ag13 in berr# berr# ab22 in/out binit# binit# aa15 in/out bnr# bnr# u17 in/out bpm0# bpm0# ad22 in/out bpm1# bpm1# ac25 in/out bpm2# bpm2# ae23 in/out bpm3# bpm3# ac23 in/out bpm4# bpm4# ad24 in/out bpm5# bpm5# ab24 in/out bpri# bpri# ae19 in br0# breq0# af16 in/out br1# breq1# ad16 in br2# breq2# ab18 in br3# breq3# af18 in cpupres# cpupres# ag15 out power pod signal d000# d00# c07 in/out d001# d01# e03 in/out d002# d02# c05 in/out d003# d03# d04 in/out d004# d04# d02 in/out d005# d05# d06 in/out d006# d06# f06 in/out d007# d07# f02 in/out d008# d08# g05 in/out d009# d09# h06 in/out d010# d10# e07 in/out d011# d11# h02 in/out d012# d12# h04 in/out d013# d13# j03 in/out table 3-1. pin/signal information sorted by pin name (sheet 2 of 15) pin name system bus signal name pin location input/output notes
38 dual-core intel ? itanium ? processor 9000 and 9100 series datasheet pinout specifications d014# d14# g03 in/out d015# d15# g07 in/out d016# d16# k04 in/out d017# d17# l03 in/out d018# d18# k06 in/out d019# d19# l05 in/out d020# d20# m02 in/out d021# d21# l07 in/out d022# d22# n07 in/out d023# d23# n03 in/out d024# d24# p04 in/out d025# d25# r03 in/out d026# d26# p06 in/out d027# d27# p02 in/out d028# d28# m06 in/out d029# d29# r05 in/out d030# d30# t02 in/out d031# d31# r07 in/out d032# d32# h10 in/out d033# d33# c11 in/out d034# d34# d10 in/out d035# d35# c09 in/out d036# d36# d12 in/out d037# d37# d08 in/out d038# d38# g09 in/out d039# d39# e13 in/out d040# d40# e09 in/out d041# d41# g11 in/out d042# d42# h08 in/out d043# d43# g13 in/out d044# d44# f12 in/out d045# d45# f08 in/out d046# d46# h12 in/out d047# d47# j13 in/out d048# d48# m08 in/out d049# d49# k08 in/out d050# d50# k10 in/out d051# d51# m12 in/out d052# d52# l13 in/out d053# d53# l09 in/out d054# d54# p08 in/out d055# d55# n13 in/out d056# d56# l11 in/out d057# d57# p12 in/out table 3-1. pin/signal information sorted by pin name (sheet 3 of 15) pin name system bus signal name pin location input/output notes
dual-core intel ? itanium ? processor 9000 and 9100 series datasheet 39 pinout specifications d058# d58# n09 in/out d059# d59# r13 in/out d060# d60# r11 in/out d061# d61# p10 in/out d062# d62# t12 in/out d063# d63# r09 in/out d064# d64# d18 in/out d065# d65# d14 in/out d066# d66# d16 in/out d067# d67# e15 in/out d068# d68# f14 in/out d069# d69# f18 in/out d070# d70# c19 in/out d071# d71# g15 in/out d072# d72# g17 in/out d073# d73# c17 in/out d074# d74# e19 in/out d075# d75# h14 in/out d076# d76# h16 in/out d077# d77# h18 in/out d078# d78# j15 in/out d079# d79# g19 in/out d080# d80# k18 in/out d081# d81# l15 in/out d082# d82# l19 in/out d083# d83# k16 in/out d084# d84# m14 in/out d085# d85# n19 in/out d086# d86# m18 in/out d087# d87# p14 in/out d088# d88# l17 in/out d089# d89# r17 in/out d090# d90# r19 in/out d091# d91# n15 in/out d092# d92# r15 in/out d093# d93# p16 in/out d094# d94# t14 in/out d095# d95# p18 in/out d096# d96# e21 in/out d097# d97# c23 in/out d098# d98# d22 in/out d099# d99# c21 in/out d100# d100# e25 in/out d101# d101# g21 in/out table 3-1. pin/signal information sorted by pin name (sheet 4 of 15) pin name system bus signal name pin location input/output notes
40 dual-core intel ? itanium ? processor 9000 and 9100 series datasheet pinout specifications d102# d102# d20 in/out d103# d103# f24 in/out d104# d104# d24 in/out d105# d105# h22 in/out d106# d106# f20 in/out d107# d107# g25 in/out d108# d108# g23 in/out d109# d109# h24 in/out d110# d110# j25 in/out d111# d111# h20 in/out d112# d112# l21 in/out d113# d113# l25 in/out d114# d114# k22 in/out d115# d115# m24 in/out d116# d116# l23 in/out d117# d117# k20 in/out d118# d118# m20 in/out d119# d119# n25 in/out d120# d120# p24 in/out d121# d121# r25 in/out d122# d122# p20 in/out d123# d123# t24 in/out d124# d124# r21 in/out d125# d125# p22 in/out d126# d126# r23 in/out d127# d127# n21 in/out dbsy# dbsy# ac09 in/out dbsy0# dbsy_c1# aa09 out dbsy1# dbsy_c2# aa19 out defer# defer# ab14 in dep00# dep0# j07 in/out dep01# dep1# j05 in/out dep02# dep2# t06 in/out dep03# dep3# t04 in/out dep04# dep4# j09 in/out dep05# dep5# j11 in/out dep06# dep6# t08 in/out dep07# dep7# t10 in/out dep08# dep8# j19 in/out dep09# dep9# j17 in/out dep10# dep10# t18 in/out dep11# dep11# t16 in/out dep12# dep12# j21 in/out dep13# dep13# j23 in/out table 3-1. pin/signal information sorted by pin name (sheet 5 of 15) pin name system bus signal name pin location input/output notes
dual-core intel ? itanium ? processor 9000 and 9100 series datasheet 41 pinout specifications dep14# dep14# t20 in/out dep15# dep15# t22 in/out drdy# drdy# ac11 in/out drdy0# drdy_c1# aa07 out drdy1# drdy_c2# aa21 out ferr# ferr# ah25 out gnd gnd a01 in gnd gnd a03 in gnd gnd a05 in gnd gnd a08 in gnd gnd a13 in gnd gnd a16 in gnd gnd a19 in gnd gnd a20 in gnd gnd a23 in gnd gnd a24 in gnd gnd aa02 in gnd gnd aa20 in gnd gnd aa24 in gnd gnd ab01 in gnd gnd ab03 in gnd gnd ab05 in gnd gnd ab07 in gnd gnd ab09 in gnd gnd ab11 in gnd gnd ab13 in gnd gnd ab15 in gnd gnd ab17 in gnd gnd ab19 in gnd gnd ab21 in gnd gnd ab23 in gnd gnd ab25 in gnd gnd ac02 in gnd gnd ac24 in gnd gnd ad01 in gnd gnd ad03 in gnd gnd ad05 in gnd gnd ad07 in gnd gnd ad09 in gnd gnd ad11 in gnd gnd ad13 in gnd gnd ad15 in gnd gnd ad17 in gnd gnd ad19 in table 3-1. pin/signal information sorted by pin name (sheet 6 of 15) pin name system bus signal name pin location input/output notes
42 dual-core intel ? itanium ? processor 9000 and 9100 series datasheet pinout specifications gnd gnd ad21 in gnd gnd ad23 in gnd gnd ad25 in gnd gnd ae02 in gnd gnd ae24 in gnd gnd af01 in gnd gnd af05 in gnd gnd af07 in gnd gnd af09 in gnd gnd af11 in gnd gnd af13 in gnd gnd af15 in gnd gnd af17 in gnd gnd af19 in gnd gnd af21 in gnd gnd ag02 in gnd gnd ag04 in gnd gnd ag06 in gnd gnd ag08 in gnd gnd ag10 in gnd gnd ag12 in gnd gnd ag14 in gnd gnd ag16 in gnd gnd ag18 in gnd gnd ag20 in gnd gnd ag22 in gnd gnd ag24 in gnd gnd ah01 in gnd gnd b03 in gnd gnd b05 in gnd gnd b07 in gnd gnd b09 in gnd gnd b10 in gnd gnd b11 in gnd gnd b13 in gnd gnd b15 in gnd gnd b17 in gnd gnd b19 in gnd gnd b21 in gnd gnd b23 in gnd gnd b25 in gnd gnd c02 in gnd gnd c06 in gnd gnd c10 in table 3-1. pin/signal information sorted by pin name (sheet 7 of 15) pin name system bus signal name pin location input/output notes
dual-core intel ? itanium ? processor 9000 and 9100 series datasheet 43 pinout specifications gnd gnd c14 in gnd gnd c18 in gnd gnd c22 in gnd gnd d01 in gnd gnd d03 in gnd gnd d05 in gnd gnd d07 in gnd gnd d09 in gnd gnd d11 in gnd gnd d13 in gnd gnd d15 in gnd gnd d17 in gnd gnd d19 in gnd gnd d21 in gnd gnd d23 in gnd gnd d25 in gnd gnd e04 in gnd gnd e08 in gnd gnd e12 in gnd gnd e16 in gnd gnd e20 in gnd gnd e24 in gnd gnd f01 in gnd gnd f03 in gnd gnd f05 in gnd gnd f07 in gnd gnd f09 in gnd gnd f11 in gnd gnd f13 in gnd gnd f15 in gnd gnd f17 in gnd gnd f19 in gnd gnd f21 in gnd gnd f23 in gnd gnd f25 in gnd gnd g02 in gnd gnd h03 in gnd gnd h05 in gnd gnd h07 in gnd gnd h09 in gnd gnd h11 in gnd gnd h13 in gnd gnd h15 in gnd gnd h17 in table 3-1. pin/signal information sorted by pin name (sheet 8 of 15) pin name system bus signal name pin location input/output notes
44 dual-core intel ? itanium ? processor 9000 and 9100 series datasheet pinout specifications gnd gnd h19 in gnd gnd h21 in gnd gnd h23 in gnd gnd h25 in gnd gnd j01 in gnd gnd j04 in gnd gnd j08 in gnd gnd j12 in gnd gnd j16 in gnd gnd j20 in gnd gnd j24 in gnd gnd k03 in gnd gnd k05 in gnd gnd k07 in gnd gnd k09 in gnd gnd k11 in gnd gnd k13 in gnd gnd k15 in gnd gnd k17 in gnd gnd k19 in gnd gnd k21 in gnd gnd k23 in gnd gnd k25 in gnd gnd l02 in gnd gnd m01 in gnd gnd m03 in gnd gnd m05 in gnd gnd m07 in gnd gnd m09 in gnd gnd m11 in gnd gnd m13 in gnd gnd m15 in gnd gnd m17 in gnd gnd m19 in gnd gnd m21 in gnd gnd m23 in gnd gnd m25 in gnd gnd n04 in gnd gnd n20 in gnd gnd n24 in gnd gnd p01 in gnd gnd p03 in gnd gnd p05 in gnd gnd p07 in table 3-1. pin/signal information sorted by pin name (sheet 9 of 15) pin name system bus signal name pin location input/output notes
dual-core intel ? itanium ? processor 9000 and 9100 series datasheet 45 pinout specifications gnd gnd p09 in gnd gnd p11 in gnd gnd p13 in gnd gnd p15 in gnd gnd p17 in gnd gnd p19 in gnd gnd p21 in gnd gnd p23 in gnd gnd p25 in gnd gnd r02 in gnd gnd t01 in gnd gnd t03 in gnd gnd t05 in gnd gnd t07 in gnd gnd t09 in gnd gnd t11 in gnd gnd t13 in gnd gnd t15 in gnd gnd t17 in gnd gnd t19 in gnd gnd t21 in gnd gnd t23 in gnd gnd t25 in gnd gnd u04 in gnd gnd u20 in gnd gnd u24 in gnd gnd v01 in gnd gnd v03 in gnd gnd v05 in gnd gnd v07 in gnd gnd v09 in gnd gnd v11 in gnd gnd v13 in gnd gnd v15 in gnd gnd v17 in gnd gnd v19 in gnd gnd v21 in gnd gnd v23 in gnd gnd v25 in gnd gnd w02 in gnd gnd y01 in gnd gnd y03 in gnd gnd y05 in gnd gnd y07 in table 3-1. pin/signal information sorted by pin name (sheet 10 of 15) pin name system bus signal name pin location input/output notes
46 dual-core intel ? itanium ? processor 9000 and 9100 series datasheet pinout specifications gnd gnd y09 in gnd gnd y11 in gnd gnd y13 in gnd gnd y15 in gnd gnd y17 in gnd gnd y19 in gnd gnd y21 in gnd gnd y23 in gnd gnd y25 in gseq# gseq# ad14 in hit# hit# ab10 in/out hitm# hitm# ab12 in/out id0# ida0#/ip0# ad02 in id1# ida1#/ip1# ab02 in id2# ida2#/dhit# ac03 in id3# ida3#/idb3# aa03 in id4# ida4#/idb4# ad04 in id5# ida5#/idb5# ab04 in id6# ida6#/idb6# ae05 in id7# ida7#/idb7# ac05 in id8# ida8#/idb8# ad06 in id9# ida9#/idb9# ab06 in ids# ids# ac07 in ignne# ignne# ag23 n/c init# init# af08 in lint0 int af22 in lint1 nmi af24 in lock# lock# ae15 n/c n/c a04 n/c ab16 n/c ac17 n/c ac21 n/c ad18 n/c ae17 n/c ag05 n/c ag11 n/c ag17 n/c ag19 n/c ag21 n/c ah05 n/c ah11 n/c ah17 n/c ah19 n/c ah21 table 3-1. pin/signal information so rted by pin name (sheet 11 of 15) pin name system bus signal name pin location input/output notes
dual-core intel ? itanium ? processor 9000 and 9100 series datasheet 47 pinout specifications n/c b04 n/c b06 n/c b08 n/c b14 n/c b16 n/c b20 n/c c03 n/c c13 n/c c15 n/c c25 n/c k02 n/c k12 n/c k14 n/c k24 n/c u05 n/c u11 outen outen af04 in power pod signal pmi# pmi# ae25 in ppodgd# ppodgd# af20 out power pod signal pwrgood pwrgood ah15 in req0# reqa0#/len0# ae09 in/out req1# wsnp#, d/c#/len1# af10 in/out req2# reqa2#/ reqb2# ad10 in/out req3# asz0#/dsz0# ae11 in/out req4# asz1#/dsz1# af12 in/out req5# req5# ad12 in/out reset# reset# ad20 in rp# rp# ac13 in/out rs0# rs0# ae07 in rs1# rs1# ad08 in rs2# rs2# ab08 in rsp# rsp# af06 in sbsy# sbsy# ae13 in/out sbsy0# sbsy_c1# aa13 out sbsy1# sbsy_c2# ac19 out sma0 sma0 b18 in smbus signal sma1 sma1 a17 in smbus signal sma2 sma2 a15 in smbus signal smsc smsc b24 in smbus signal smsd smsd b22 in/out smbus signal smwp smwp a21 in smbus signal stbn0# stbn0# f04 in/out stbn1# stbn1# n05 in/out stbn2# stbn2# f10 in/out table 3-1. pin/signal information sorted by pin name (sheet 12 of 15) pin name system bus signal name pin location input/output notes
48 dual-core intel ? itanium ? processor 9000 and 9100 series datasheet pinout specifications stbn3# stbn3# n11 in/out stbn4# stbn4# f16 in/out stbn5# stbn5# n17 in/out stbn6# stbn6# f22 in/out stbn7# stbn7# n23 in/out stbp0# stbp0# e05 in/out stbp1# stbp1# m04 in/out stbp2# stbp2# e11 in/out stbp3# stbp3# m10 in/out stbp4# stbp4# e17 in/out stbp5# stbp5# m16 in/out stbp6# stbp6# e23 in/out stbp7# stbp7# m22 in/out tck tck ag09 in jtag tdi tdi ag07 in jtag tdo tdo ah07 out jtag terma fsbt1 af02 in termb fsbt2 ae03 in thrmtrip# thrmtrip# ag25 out thrmalert# thrmalert# a07 out tms tms ah09 in jtag tnd# tnd# ac15 in/out trdy# trdy# af14 in trst# trst# ae21 in jtag tuner[1] tuner[1] ah03 in tuner[2] tuner[2] ag03 in tuner[3] tuner[3] b08 in vccmon vccmon a11 n/c vcterm vcterm a02 in vcterm vcterm a06 in vcterm vcterm a10 in vcterm vcterm a14 in vcterm vcterm a18 in vcterm vcterm a22 in vcterm vcterm a25 in vcterm vcterm c01 in vcterm vcterm c04 in vcterm vcterm c08 in vcterm vcterm c12 in vcterm vcterm c16 in vcterm vcterm c20 in vcterm vcterm c24 in vcterm vcterm e02 in vcterm vcterm e06 in table 3-1. pin/signal information so rted by pin name (sheet 13 of 15) pin name system bus signal name pin location input/output notes
dual-core intel ? itanium ? processor 9000 and 9100 series datasheet 49 pinout specifications vcterm vcterm e10 in vcterm vcterm e14 in vcterm vcterm e18 in vcterm vcterm e22 in vcterm vcterm g01 in vcterm vcterm g04 in vcterm vcterm g08 in vcterm vcterm g12 in vcterm vcterm g16 in vcterm vcterm g20 in vcterm vcterm g24 in vcterm vcterm j02 in vcterm vcterm j06 in vcterm vcterm j10 in vcterm vcterm j14 in vcterm vcterm j18 in vcterm vcterm j22 in vcterm vcterm l01 in vcterm vcterm l04 in vcterm vcterm l08 in vcterm vcterm l12 in vcterm vcterm l16 in vcterm vcterm l20 in vcterm vcterm l24 in vcterm vcterm n02 in vcterm vcterm n06 in vcterm vcterm n10 in vcterm vcterm n14 in vcterm vcterm n18 in vcterm vcterm n22 in vcterm vcterm r01 in vcterm vcterm r04 in vcterm vcterm r08 in vcterm vcterm r12 in vcterm vcterm r16 in vcterm vcterm r20 in vcterm vcterm r24 in vcterm vcterm u02 in vcterm vcterm u06 in vcterm vcterm u10 in vcterm vcterm u14 in vcterm vcterm u18 in vcterm vcterm u22 in table 3-1. pin/signal information sorted by pin name (sheet 14 of 15) pin name system bus signal name pin location input/output notes
50 dual-core intel ? itanium ? processor 9000 and 9100 series datasheet pinout specifications vcterm vcterm u25 in vssmon vssmon a09 n/c table 3-2. pin/signal information sorted by pin location (sheet 1 of 15) pin name system bus signal name pin location input/output notes gnd gnd a01 in vcterm vcterm a02 in gnd gnd a03 in n/c a04 gnd gnd a05 in vcterm vcterm a06 in thrmalert# thrmalert# a07 out gnd gnd a08 in vssmon vssmon a09 n/c vcterm vcterm a10 in vccmon vccmon a11 n/c gnd gnd a13 in vcterm vcterm a14 in sma2 sma2 a15 in smbus signal gnd gnd a16 in sma1 sma1 a17 in smbus signal vcterm vcterm a18 in gnd gnd a19 in gnd gnd a20 in smwp smwp a21 in smbus signal vcterm vcterm a22 in gnd gnd a23 in gnd gnd a24 in vcterm vcterm a25 in 3.3v b02 in smbus supply voltage gnd gnd b03 in n/c b04 gnd gnd b05 in n/c b06 gnd gnd b07 in tuner[3] tuner[3] b08 in gnd gnd b09 in gnd gnd b10 in gnd gnd b11 in gnd gnd b13 in n/c b14 gnd gnd b15 in n/c b16 table 3-1. pin/signal information so rted by pin name (sheet 15 of 15) pin name system bus signal name pin location input/output notes
dual-core intel ? itanium ? processor 9000 and 9100 series datasheet 51 pinout specifications gnd gnd b17 in sma0 sma0 b18 in smbus signal gnd gnd b19 in n/c b20 gnd gnd b21 in smsd smsd b22 in/out smbus signal gnd gnd b23 in smsc smsc b24 in smbus signal gnd gnd b25 in vcterm vcterm c01 in gnd gnd c02 in n/c c03 vcterm vcterm c04 in d002# d02# c05 in/out gnd gnd c06 in d000# d00# c07 in/out vcterm vcterm c08 in d035# d35# c09 in/out gnd gnd c10 in d033# d33# c11 in/out vcterm vcterm c12 in n/c c13 gnd gnd c14 in n/c c15 vcterm vcterm c16 in d073# d73# c17 in/out gnd gnd c18 in d070# d70# c19 in/out vcterm vcterm c20 in d099# d99# c21 in/out gnd gnd c22 in d097# d97# c23 in/out vcterm vcterm c24 in n/c c25 gnd gnd d01 in d004# d04# d02 in/out gnd gnd d03 in d003# d03# d04 in/out gnd gnd d05 in d005# d05# d06 in/out gnd gnd d07 in d037# d37# d08 in/out gnd gnd d09 in d034# d34# d10 in/out table 3-2. pin/signal information so rted by pin location (sheet 2 of 15) pin name system bus signal name pin location input/output notes
52 dual-core intel ? itanium ? processor 9000 and 9100 series datasheet pinout specifications gnd gnd d11 in d036# d36# d12 in/out gnd gnd d13 in d065# d65# d14 in/out gnd gnd d15 in d066# d66# d16 in/out gnd gnd d17 in d064# d64# d18 in/out gnd gnd d19 in d102# d102# d20 in/out gnd gnd d21 in d098# d98# d22 in/out gnd gnd d23 in d104# d104# d24 in/out gnd gnd d25 in vcterm vcterm e02 in d001# d01# e03 in/out gnd gnd e04 in stbp0# stbp0# e05 in/out vcterm vcterm e06 in d010# d10# e07 in/out gnd gnd e08 in d040# d40# e09 in/out vcterm vcterm e10 in stbp2# stbp2# e11 in/out gnd gnd e12 in d039# d39# e13 in/out vcterm vcterm e14 in d067# d67# e15 in/out gnd gnd e16 in stbp4# stbp4# e17 in/out vcterm vcterm e18 in d074# d74# e19 in/out gnd gnd e20 in d096# d96# e21 in/out vcterm vcterm e22 in stbp6# stbp6# e23 in/out gnd gnd e24 in d100# d100# e25 in/out gnd gnd f01 in d007# d07# f02 in/out gnd gnd f03 in stbn0# stbn0# f04 in/out gnd gnd f05 in table 3-2. pin/signal information sorted by pin location (sheet 3 of 15) pin name system bus signal name pin location input/output notes
dual-core intel ? itanium ? processor 9000 and 9100 series datasheet 53 pinout specifications d006# d06# f06 in/out gnd gnd f07 in d045# d45# f08 in/out gnd gnd f09 in stbn2# stbn2# f10 in/out gnd gnd f11 in d044# d44# f12 in/out gnd gnd f13 in d068# d68# f14 in/out gnd gnd f15 in stbn4# stbn4# f16 in/out gnd gnd f17 in d069# d69# f18 in/out gnd gnd f19 in d106# d106# f20 in/out gnd gnd f21 in stbn6# stbn6# f22 in/out gnd gnd f23 in d103# d103# f24 in/out gnd gnd f25 in vcterm vcterm g01 in gnd gnd g02 in d014# d14# g03 in/out vcterm vcterm g04 in d008# d08# g05 in/out d015# d15# g07 in/out vcterm vcterm g08 in d038# d38# g09 in/out d041# d41# g11 in/out vcterm vcterm g12 in d043# d43# g13 in/out d071# d71# g15 in/out vcterm vcterm g16 in d072# d72# g17 in/out d079# d79# g19 in/out vcterm vcterm g20 in d101# d101# g21 in/out d108# d108# g23 in/out vcterm vcterm g24 in d107# d107# g25 in/out d011# d11# h02 in/out gnd gnd h03 in d012# d12# h04 in/out gnd gnd h05 in table 3-2. pin/signal information so rted by pin location (sheet 4 of 15) pin name system bus signal name pin location input/output notes
54 dual-core intel ? itanium ? processor 9000 and 9100 series datasheet pinout specifications d009# d09# h06 in/out gnd gnd h07 in d042# d42# h08 in/out gnd gnd h09 in d032# d32# h10 in/out gnd gnd h11 in d046# d46# h12 in/out gnd gnd h13 in d075# d75# h14 in/out gnd gnd h15 in d076# d76# h16 in/out gnd gnd h17 in d077# d77# h18 in/out gnd gnd h19 in d111# d111# h20 in/out gnd gnd h21 in d105# d105# h22 in/out gnd gnd h23 in d109# d109# h24 in/out gnd gnd h25 in gnd gnd j01 in vcterm vcterm j02 in d013# d13# j03 in/out gnd gnd j04 in dep01# dep1# j05 in/out vcterm vcterm j06 in dep00# dep0# j07 in/out gnd gnd j08 in dep04# dep4# j09 in/out vcterm vcterm j10 in dep05# dep5# j11 in/out gnd gnd j12 in d047# d47# j13 in/out vcterm vcterm j14 in d078# d78# j15 in/out gnd gnd j16 in dep09# dep9# j17 in/out vcterm vcterm j18 in dep08# dep8# j19 in/out gnd gnd j20 in dep12# dep12# j21 in/out vcterm vcterm j22 in dep13# dep13# j23 in/out gnd gnd j24 in table 3-2. pin/signal information sorted by pin location (sheet 5 of 15) pin name system bus signal name pin location input/output notes
dual-core intel ? itanium ? processor 9000 and 9100 series datasheet 55 pinout specifications d110# d110# j25 in/out n/c k02 gnd gnd k03 in d016# d16# k04 in/out gnd gnd k05 in d018# d18# k06 in/out gnd gnd k07 in d049# d49# k08 in/out gnd gnd k09 in d050# d50# k10 in/out gnd gnd k11 in n/c k12 gnd gnd k13 in n/c k14 gnd gnd k15 in d083# d83# k16 in/out gnd gnd k17 in d080# d80# k18 in/out gnd gnd k19 in d117# d117# k20 in/out gnd gnd k21 in d114# d114# k22 in/out gnd gnd k23 in n/c k24 gnd gnd k25 in vcterm vcterm l01 in gnd gnd l02 in d017# d17# l03 in/out vcterm vcterm l04 in d019# d19# l05 in/out d021# d21# l07 in/out vcterm vcterm l08 in d053# d53# l09 in/out d056# d56# l11 in/out vcterm vcterm l12 in d052# d52# l13 in/out d081# d81# l15 in/out vcterm vcterm l16 in d088# d88# l17 in/out d082# d82# l19 in/out vcterm vcterm l20 in d112# d112# l21 in/out d116# d116# l23 in/out vcterm vcterm l24 in table 3-2. pin/signal information so rted by pin location (sheet 6 of 15) pin name system bus signal name pin location input/output notes
56 dual-core intel ? itanium ? processor 9000 and 9100 series datasheet pinout specifications d113# d113# l25 in/out gnd gnd m01 in d020# d20# m02 in/out gnd gnd m03 in stbp1# stbp1# m04 in/out gnd gnd m05 in d028# d28# m06 in/out gnd gnd m07 in d048# d48# m08 in/out gnd gnd m09 in stbp3# stbp3# m10 in/out gnd gnd m11 in d051# d51# m12 in/out gnd gnd m13 in d084# d84# m14 in/out gnd gnd m15 in stbp5# stbp5# m16 in/out gnd gnd m17 in d086# d86# m18 in/out gnd gnd m19 in d118# d118# m20 in/out gnd gnd m21 in stbp7# stbp7# m22 in/out gnd gnd m23 in d115# d115# m24 in/out gnd gnd m25 in vcterm vcterm n02 in d023# d23# n03 in/out gnd gnd n04 in stbn1# stbn1# n05 in/out vcterm vcterm n06 in d022# d22# n07 in/out d058# d58# n09 in/out vcterm vcterm n10 in stbn3# stbn3# n11 in/out d055# d55# n13 in/out vcterm vcterm n14 in d091# d91# n15 in/out stbn5# stbn5# n17 in/out vcterm vcterm n18 in d085# d85# n19 in/out gnd gnd n20 in d127# d127# n21 in/out vcterm vcterm n22 in table 3-2. pin/signal information sorted by pin location (sheet 7 of 15) pin name system bus signal name pin location input/output notes
dual-core intel ? itanium ? processor 9000 and 9100 series datasheet 57 pinout specifications stbn7# stbn7# n23 in/out gnd gnd n24 in d119# d119# n25 in/out gnd gnd p01 in d027# d27# p02 in/out gnd gnd p03 in d024# d24# p04 in/out gnd gnd p05 in d026# d26# p06 in/out gnd gnd p07 in d054# d54# p08 in/out gnd gnd p09 in d061# d61# p10 in/out gnd gnd p11 in d057# d57# p12 in/out gnd gnd p13 in d087# d87# p14 in/out gnd gnd p15 in d093# d93# p16 in/out gnd gnd p17 in d095# d95# p18 in/out gnd gnd p19 in d122# d122# p20 in/out gnd gnd p21 in d125# d125# p22 in/out gnd gnd p23 in d120# d120# p24 in/out gnd gnd p25 in vcterm vcterm r01 in gnd gnd r02 in d025# d25# r03 in/out vcterm vcterm r04 in d029# d29# r05 in/out d031# d31# r07 in/out vcterm vcterm r08 in d063# d63# r09 in/out d060# d60# r11 in/out vcterm vcterm r12 in d059# d59# r13 in/out d092# d92# r15 in/out vcterm vcterm r16 in d089# d89# r17 in/out d090# d90# r19 in/out vcterm vcterm r20 in table 3-2. pin/signal information so rted by pin location (sheet 8 of 15) pin name system bus signal name pin location input/output notes
58 dual-core intel ? itanium ? processor 9000 and 9100 series datasheet pinout specifications d124# d124# r21 in/out d126# d126# r23 in/out vcterm vcterm r24 in d121# d121# r25 in/out gnd gnd t01 in d030# d30# t02 in/out gnd gnd t03 in dep03# dep3# t04 in/out gnd gnd t05 in dep02# dep2# t06 in/out gnd gnd t07 in dep06# dep6# t08 in/out gnd gnd t09 in dep07# dep7# t10 in/out gnd gnd t11 in d062# d62# t12 in/out gnd gnd t13 in d094# d94# t14 in/out gnd gnd t15 in dep11# dep11# t16 in/out gnd gnd t17 in dep10# dep10# t18 in/out gnd gnd t19 in dep14# dep14# t20 in/out gnd gnd t21 in dep15# dep15# t22 in/out gnd gnd t23 in d123# d123# t24 in/out gnd gnd t25 in vcterm vcterm u02 in a005# aa05#/exf2# u03 in/out gnd gnd u04 in n/c u05 vcterm vcterm u06 in a009# aa09#/be1# u07 in/out a018# aa18#/did2# u09 in/out vcterm vcterm u10 in n/c u11 a016# aa16#/did0# u13 in/out vcterm vcterm u14 in a028# aa28#/xtprvalue1# u15 in/out bnr# bnr# u17 in/out vcterm vcterm u18 in a027# aa27#/xtprvalue0# u19 in/out table 3-2. pin/signal information sorted by pin location (sheet 9 of 15) pin name system bus signal name pin location input/output notes
dual-core intel ? itanium ? processor 9000 and 9100 series datasheet 59 pinout specifications gnd gnd u20 in a048# aa48#/ab48# u21 in/out vcterm vcterm u22 in a042# aa42#/ab42# u23 in/out gnd gnd u24 in vcterm vcterm u25 in gnd gnd v01 in a004# aa04#/exf1# v02 in/out gnd gnd v03 in a010# aa10#/be2# v04 in/out gnd gnd v05 in a003# aa03#/exf0# v06 in/out gnd gnd v07 in a015# aa15#/be7# v08 in/out gnd gnd v09 in a020# aa20#/did4# v10 in/out gnd gnd v11 in a019# aa19#/did3# v12 in/out gnd gnd v13 in a031# aa31#/xtprdisable# v14 in/out gnd gnd v15 in a038# aa38#/ab38# v16 in/out gnd gnd v17 in a029# aa29#/xtprvalue2# v18 in/out gnd gnd v19 in a045# aa45#/ab45# v20 in/out gnd gnd v21 in a047# aa47#/ab47# v22 in/out gnd gnd v23 in a040# aa40#/ab40# v24 in/out gnd gnd v25 in gnd gnd w02 in a006# aa06#/exf3# w03 in/out a012# aa12#/be4# w05 in/out a014# aa14#/be6# w07 in/out a021# aa21#/did5# w09 in/out a026# aa26#/ab26# w11 in/out a022# aa22#/did6# w13 in/out a037# aa37#/ab37# w15 in/out a032# aa32#/attr0# w17 in/out a030# aa30#/xtprvalue3# w19 in/out a044# aa44#/ab44# w21 in/out a046# aa46#/ab46# w23 in/out a041# aa41#/ab41# w25 in/out table 3-2. pin/signal information sort ed by pin location (sheet 10 of 15) pin name system bus signal name pin location input/output notes
60 dual-core intel ? itanium ? processor 9000 and 9100 series datasheet pinout specifications gnd gnd y01 in a007# aa07#/exf4# y02 in/out gnd gnd y03 in a013# aa13#/be5# y04 in/out gnd gnd y05 in a008# aa08#/be0# y06 in/out gnd gnd y07 in a017# aa17#/did1# y08 in/out gnd gnd y09 in a024# aa24#/did8# y10 in/out gnd gnd y11 in a025# aa25#/did9# y12 in/out gnd gnd y13 in a034# aa34#/attr2# y14 in/out gnd gnd y15 in a036# aa36#/ab36# y16 in/out gnd gnd y17 in a035# aa35#/attr3# y18 in/out gnd gnd y19 in a039# aa39#/ab39# y20 in/out gnd gnd y21 in a049# aa49#/ab49# y22 in/out gnd gnd y23 in a043# aa43#/ab43# y24 in/out gnd gnd y25 in gnd gnd aa02 in id3# ida3#/idb3# aa03 in a011# aa11#/be3# aa05 in/out drdy0# drdy_c1# aa07 out dbsy0# dbsy_c1# aa09 out a023# aa23#/did7# aa11 in/out sbsy0# sbsy_c1# aa13 out binit# binit# aa15 in/out a033# aa33#/attr1# aa17 in/out dbsy1# dbsy_c2# aa19 out gnd gnd aa20 in drdy1# drdy_c2# aa21 out ap1# ap1# aa23 in/out gnd gnd aa24 in ap0# ap0# aa25 in/out gnd gnd ab01 in id1# ida1#/ip1# ab02 in gnd gnd ab03 in id5# ida5#/idb5# ab04 in table 3-2. pin/signal information sorted by pin location (sheet 11 of 15) pin name system bus signal name pin location input/output notes
dual-core intel ? itanium ? processor 9000 and 9100 series datasheet 61 pinout specifications gnd gnd ab05 in id9# ida9#/idb9# ab06 in gnd gnd ab07 in rs2# rs2# ab08 in gnd gnd ab09 in hit# hit# ab10 in/out gnd gnd ab11 in hitm# hitm# ab12 in/out gnd gnd ab13 in defer# defer# ab14 in gnd gnd ab15 in n/c ab16 gnd gnd ab17 in br2# breq2# ab18 in gnd gnd ab19 in ads# ads# ab20 in/out gnd gnd ab21 in berr# berr# ab22 in/out gnd gnd ab23 in bpm5# bpm5# ab24 in/out gnd gnd ab25 in gnd gnd ac02 in id2# ida2#/dhit# ac03 in id7# ida7#/idb7# ac05 in ids# ids# ac07 in dbsy# dbsy# ac09 in/out drdy# drdy# ac11 in/out rp# rp# ac13 in/out tnd# tnd# ac15 in/out n/c ac17 sbsy1# sbsy_c2# ac19 out n/c# ac21 bpm3# bpm3# ac23 in/out gnd gnd ac24 in bpm1# bpm1# ac25 in/out gnd gnd ad01 in id0# ida0#/ip0# ad02 in gnd gnd ad03 in id4# ida4#/idb4# ad04 in gnd gnd ad05 in id8# ida8#/idb8# ad06 in gnd gnd ad07 in rs1# rs1# ad08 in gnd gnd ad09 in table 3-2. pin/signal information sort ed by pin location (sheet 12 of 15) pin name system bus signal name pin location input/output notes
62 dual-core intel ? itanium ? processor 9000 and 9100 series datasheet pinout specifications req2# reqa2#/ reqb2# ad10 in/out gnd gnd ad11 in req5# req5# ad12 in/out gnd gnd ad13 in gseq# gseq# ad14 in gnd gnd ad15 in br1# breq1# ad16 in gnd gnd ad17 in n/c ad18 gnd gnd ad19 in reset# reset# ad20 in gnd gnd ad21 in bpm0# bpm0# ad22 in/out gnd gnd ad23 in bpm4# bpm4# ad24 in/out gnd gnd ad25 in gnd gnd ae02 in termb fsbt2 ae03 id6# ida6#/idb6# ae05 in rs0# rs0# ae07 in req0# reqa0#/len0# ae09 in/out req3# asz0#/dsz0# ae11 in/out sbsy# sbsy# ae13 in/out lock# lock# ae15 n/c n/c ae17 bpri# bpri# ae19 in trst# trst# ae21 in bpm2# bpm2# ae23 in/out gnd gnd ae24 in pmi# pmi# ae25 in gnd gnd af01 in term fsbt af02 in outen outen af04 in power pod signal gnd gnd af05 in rsp# rsp# af06 in gnd gnd af07 in init# init# af08 in gnd gnd af09 in req1# wsnp#, d/c#/len1# af10 in/out gnd gnd af11 in req4# asz1#/dsz1# af12 in/out gnd gnd af13 in trdy# trdy# af14 in gnd gnd af15 in table 3-2. pin/signal information sorted by pin location (sheet 13 of 15) pin name system bus signal name pin location input/output notes
dual-core intel ? itanium ? processor 9000 and 9100 series datasheet 63 pinout specifications br0# breq0# af16 in/out gnd gnd af17 in br3# breq3# af18 in gnd gnd af19 in ppodgd# ppodgd# af20 out power pod signal gnd gnd af21 in lint0 int af22 in lint1 nmi af24 in gnd gnd ag02 in tuner[2] ag03 in gnd gnd ag04 in n/c ag05 gnd gnd ag06 in tdi tdi ag07 in jtag gnd gnd ag08 in tck tck ag09 in jtag gnd gnd ag10 in n/c ag11 gnd gnd ag12 in bclkp clk ag13 in gnd gnd ag14 in cpupres# cpupres# ag15 out power pod signal gnd gnd ag16 in n/c ag17 gnd gnd ag18 in n/c ag19 gnd gnd ag20 in n/c ag21 gnd gnd ag22 in ignne# ignne# ag23 n/c gnd gnd ag24 in thrmtrip# thrmtrip# ag25 out thermal trip gnd gnd ah01 in tuner[1] ah03 in n/c ah05 tdo tdo ah07 out jtag tms tms ah09 in jtag n/c ah11 bclkn bclkn ah13 in pwrgood pwrgood ah15 in n/c ah17 n/c ah19 n/c ah21 table 3-2. pin/signal information sort ed by pin location (sheet 14 of 15) pin name system bus signal name pin location input/output notes
64 dual-core intel ? itanium ? processor 9000 and 9100 series datasheet pinout specifications a20m# a20m# ah23 n/c ferr# ferr# ah25 out table 3-2. pin/signal information sorted by pin location (sheet 15 of 15) pin name system bus signal name pin location input/output notes
dual-core intel ? itanium ? processor 9000 and 9100 series datasheet 65 mechanical specifications 4 mechanical specifications this chapter provides the mechanical spec ifications of the dual-core intel itanium processor 9000 and 9100 series. 4.1 processor package dimensions figure 4-1 through figure 4-5 provide package mechanical drawings and dimensions of the processor. ta b l e 4 - 1 and ta b l e 4 - 2 provide additional details on the package dimensions. the main components of processor package are identified in figure 4-2 . all specified package dimensions are in millimeters. figure 4-1 illustrates key package mechanical feat ures. these features enable package integration with socket, power pod, and cooling solution. ? vcore, vcache, vfixed, gnd, and vid pads : contact pads for delivering power and i/o signals from the voltage regulator to the processor through its substrate. ? socket alignment keyways : they define package position in x and y direction with respect to socket for proper alignment of package pins to socket contact holes. ? pin shroud alignment keyways : they define pin shroud position in x and y direction with respect to processor. ? pin 1 indicators : identifies package orientation with respect to socket and motherboard. ? integrated heat spreader (ihs) : enhances dissipation of heat generated by the processor. provides interface surface between processor and cooling solution. ? substrate : processor mechanical and electrical integration vehicle with the motherboard and processor enabling components. ? pin field (grid) : 28 x 25 partially-filled pin field for transmitting signals to and from processor to motherboard. ? voltage regulator connector back plate keyway : it defines the vr connector back plate position in x and y direction with respect to the processor.
66 dual-core intel ? itanium ? processor 9000 and 9100 series datasheet mechanical specifications figure 4-1. processor package 001349 ihs package c l c l d 1 top view a c 2 b 2 c 1 b 1 b a1 front view a h 1 g 1 j 2 j 1 h 2 g 2 bottom view a25 ah25 ah1 a1 side view
dual-core intel ? itanium ? processor 9000 and 9100 series datasheet 67 mechanical specifications table 4-1. processor package dimensions figure 4-2. package height and pin dimensions
68 dual-core intel ? itanium ? processor 9000 and 9100 series datasheet mechanical specifications table 4-2. processor package me chanical interface dimensions
dual-core intel ? itanium ? processor 9000 and 9100 series datasheet 69 mechanical specifications figure 4-3. processor package me chanical interface dimensions
70 dual-core intel ? itanium ? processor 9000 and 9100 series datasheet mechanical specifications note: keepout zones indicate no components will be on the processor package. note: keepout zones indicate no components will be on the processor package. figure 4-4. processor package top-si de components height dimensions figure 4-5. processor package bottom -side components height dimensions
dual-core intel ? itanium ? processor 9000 and 9100 series datasheet 71 mechanical specifications 4.1.1 voltage regulator (mvr) to processor package interface critical package mechanical requirements at its interface with the mvr are identified in figure 4-6 and ta b l e 4 - 3 . the processor interface boundary conditions with which mvr must comply during and after installation are outlined in ta b l e 4 - 3 . these requirements are intended to minimize potential damage to the processor that may result from installation of the mvr. figure 4-6. processor to mvr interface loads 90 processor heatsink ihs processor heatsink 90 t z p -z p +z a t y substrate socket mother board y x z x table 4-3. processor package load limits at power tab (sheet 1 of 2) parameter description value 1 comments a final position of the package at the power tab (unloaded) with respect to system board 3.8+/- 0.1mm position of the processor power tab is based on the height of the mpga700 zif socket height from the mother post smt p allowable load on the package in +z and -z direction 22.25n max d allowable displacement at the processor power tab in z direction under load p +/- 0.3 mm max tz allowable torque on the package tip in z axis 0 package loading in y direction is not allowed. hence, zero torque in z-axis
72 dual-core intel ? itanium ? processor 9000 and 9100 series datasheet mechanical specifications 4.2 package marking the following section details the processor top-side and bottom-side markings for engineering samples and production units. this is provided to aid in identification. specific details regarding individual fields in the product markings will be furnished in a future release of this document. 4.2.1 processor top-side marking the top-side mark is a laser marking on the ihs. figure 4-7 shows the general location of the processor top-side mark that provides the following information: ?intel ? ? itanium ? processor family legal mark ? assembly process order (apo) number ?unit serial number ?2d matrix mark tx allowable torque at the package power tab in x axis 0.57nm max t+y allowable torque at the package power tab in +y direction 1.24 nm max torque on th e package edge in +y direction is determ ined by the load applied in -z and the distance from the edge the package to the socket. torque on the package edge in -y direction is determ ined by the load applied in +z and the distance from the edge the package to the heatsink base. to determine t+y, distance from the edge the package to the socket of 55.7mm is applied to determine t-y, distance from the edge the package to the heatsink pedestal of 42mm is applied t-y allowable torque at the package power tab in -y direction 0.93nm max notes: 1. load determination done with 100- lb. load on the processor heatsink. table 4-3. processor package load limits at power tab (sheet 2 of 2) parameter description value 1 comments
dual-core intel ? itanium ? processor 9000 and 9100 series datasheet 73 mechanical specifications 4.2.2 processor bottom-side marking the processor bottom-side mark for the product is a laser marking on the pin side of the interposer. figure 4-8 shows the placement of the laser marking on the pin side of interposer. the processor bottom-side ma rk provides the following information: ?product id ?s-spec ? finish process order (fpo) ? 2d matrix mark figure 4-7. processor to p-side marking on ihs
74 dual-core intel ? itanium ? processor 9000 and 9100 series datasheet mechanical specifications figure 4-8. processor bottom-side marking placement on interposer scale 2 laser marking 2d matrix mark (see notes) scale 2 laser marking 2d matrix mark (see notes)
dual-core intel ? itanium ? processor 9000 and 9100 series datasheet 75 thermal specifications 5 thermal specifications this chapter provides a description of the thermal features relating to the dual-core intel itanium processor 9000 and 9100 series. 5.1 thermal features the processor has an internal thermal circuit which senses when a certain temperature is reached on the processor core. this circuit is used for controlling various thermal states. in addition, an on-chip thermal diode is available for use by the thermal sensing device on the processor. figure 5-1 shows the relationship between temperature, time, and the thermal alert, enhanced thermal ma nagement (etm), and thermal trip points. note: figure 5-1 is not intended to show a linear rela tionship in time or temperature as a processor's thermal state advances from one state to the next state when the cooling solution fails to control the processor temperat ure, as this is affected by many factors such as cooling solution performance degradation and processor workload variations. 5.1.1 thermal alert thrmalert# is a programmable thermal alert signal which is part of the processor system management feature. thrmaler t# is asserted when the measured temperature from the processor thermal diode equals or exceeds the temperature threshold data programmed in the high temp (thigh) or low temp (tlow) registers on the sensor. intel recommends using the uppe r temperature reference byte listed in the processor information rom when pr ogramming the thigh register (see chapter 6 for more details). this signal can be used by the platform to implement thermal regulation features such as generating an external in terrupt to tell the operating system that the processor core die temperature is increasing. figure 5-1. dual-core intel ? itanium ? processor 9000 and 9100 series thermal features 000653b temperature time thermal alert thermal trip etm
76 dual-core intel ? itanium ? processor 9000 and 9100 series datasheet thermal specifications 5.1.2 enhanced thermal management etm is a power and thermal protection feature. on the dual-core intel itanium processor 9000 and 9100 series, etm uses power and thermal sensing devices on the die to monitor entry points, indicating da ngerous operation exceeding the thermal or power specification. once the sensing devi ces observe the temperature rising above the power or thermal entry point, the processor will enter a low power mode of execution and notify the system by sending a correctable machine check interrupt (cmci). the processor will remain in this low power mode until the power and temperature decrease below the entry points and remain there for approximately one second, at which point it will send another cmci and resume normal operation. if the power and temperature cannot be reduced, and continue to rise to critical levels, the processor will assert power trip or thermal trip. the etm feature may be disabled through the pal. 5.1.3 power trip the dual-core intel itanium processor 9000 and 9100 series protects itself and the mvr from catastrophic over power by use of an internal power sensor. the sensor trip point is set above the normal operating power to ensure that there are no false trips. the processor will signal a continuable mca when the power draw exceeds a safe operating level. warning: data will be lost if the mvr overheats and s huts down as a result of an extended over power condition. once power trip is activated, the processor can continue operation, but may continue to signal continuable mcas as long as the over power condition exists. 5.1.4 thermal trip the dual-core intel itanium processor 9000 and 9100 series protects itself from catastrophic overheating by use of an internal thermal sensor. the sensor trip point is set well above the normal operating temperature to ensure that there are no false trips. the processor will stop all execution when the junction temperature exceeds a safe operating level. warning: data will be lost if the processor goes into thermal trip (signaled to the system by the thrmtrip# pin). once thermal trip is activated, the processor remains stopped until reset# is asserted. the processor case temperature must drop below the specified maximum before issuing a reset to the processor. please see section 5.2 for details on case temperature. 5.2 case temperature see ta b l e 5 - 1 for the case temperature specifications for the dual-core intel itanium processor 9000 and 9100 series. the case temperature is defined as the temperature measured at the center of the top surface of the ihs. warning: data may be lost if the case temperature exceeds the specified maximum.
dual-core intel ? itanium ? processor 9000 and 9100 series datasheet 77 thermal specifications figure 5-2 contains dimensions for the thermocouple location on the processor package. this is the recommended location for placement of a thermocouple for case temperature measurement. table 5-1. case temper ature specification symbol parameter core frequency minimum maximum unit notes tcase case temperature 1.6ghz/24mb 5 76 c 1.6ghz/18mb 5 76 c 1.6ghz/9mb 5 76 c 1.42ghz/12mb 5 76 c 1.4ghz/12mb 5 76 c 1.6ghz/6mb 5 74 c figure 5-2. itanium ? processor package thermocouple location all dimensions are measured in mm. not to scale. 001103a thermocouple location 45.00 2 4.13
78 dual-core intel ? itanium ? processor 9000 and 9100 series datasheet thermal specifications
dual-core intel ? itanium ? processor 9000 and 9100 series datasheet 79 system management feature specifications 6 system management feature specifications the dual-core intel itanium processor 9000 and 9100 series includes a system management bus (smbus) interface. this ch apter describes the features of the smbus and smbus components. 6.1 system management bus 6.1.1 system management bus interface the processor includes an itanium proce ssor family smbus interface which allows access to several processor features. the system management components on the processor include two memory components (eeproms) and a thermal sensing device (digital thermometer). the processor info rmation eeprom (pirom) is programmed by intel with manufacturing and feature information specific to the dual-core intel itanium processor 9000 and 9100 series. this information is permanently write- protected. section 6.2 provides details on the pirom. the other eeprom is a scratch eeprom that is available for other data at the system vendor?s discretion. the thermal sensor can be used in conjunction with the information in the pirom and/or the scratch eeprom for system thermal monitoring an d management. the thermal sensing device on the processor provides an accurate means of acquiring an indicator of the junction temperature of the processor core die. the thermal sensing device is connected to the anode and cathode of the processor on-die thermal diode. smbus implementation on the processor uses the clock and data signals as defined by smbus specifications. 6.1.2 system management interface signals ta b l e 6 - 1 lists the system management interface signals and their descriptions. these signals are used by the system to access the system management components via the smbus. figure 6-1 shows the logical schematics of smbus circuitry on the processor and shows how the various system management components are connected to the smbus. the reference to the system board at the lower left corner of figure 6-1 shows how smbus address configuration for multiple processors can be realized with resistor stuffing options. table 6-1. system management interface signal descriptions signal name pin count description 3.3v 1 voltage supply for eeproms and thermal sensor. sma[2:0] 3 address select passed through from socket. smsc 1 system management bus clock. smsd 1 system management serial address/data bus. smwp 1 scratch eeprom write protect. thrmalert# 1 temperature alert from the thermal sensor.
80 dual-core intel ? itanium ? processor 9000 and 9100 series datasheet system management feature specifications figure 6-1. logical schematic of smbus circuitry note: 1. actual implementation may vary. 2. for use in general understa nding of the architecture. 000668b processor information rom a0 a1 a2 sc sd v cc 10k 10k 3.3v scratch eeprom a0 a1 a2 sd wp v cc sc 10k 10k 10k thermal sensing device vcc a0 a1 sc sd stby alert sma0 sma1 sma2 3.3v smsd smsc thrmalert# core thermda thermdc stuffing options 3.3v system board 10k smwp system board 3.3v 10k intel ? itanium ? 2 processor
dual-core intel ? itanium ? processor 9000 and 9100 series datasheet 81 system management feature specifications 6.1.3 smbus device addressing of the addresses broadcast across the smbus, the memory components claim those of the form ?1010xxyzb?. the ?xx? and ?y? bits are used to enable the devices on the processor at adjacent addresses. the y bit is hard-wired on the processor to gnd (?0?) for the scratch eeprom and pulled to 3.3 v (?1?) for the processor information rom. the ?xx? bits are defined by the processor socket via the sma0 and sma1 pins on the processor connector. these address pins have a weak pull-down (10 k ) to ensure that the memory components are in a known state in systems which do not support the smbus, or only support a partial implementa tion. the ?z? bit is the read/write bit for the serial bus transaction. the thermal sensing device internally decodes one of three upper address patterns from the bus of the form ?0011xxxzb?, ? 1001xxxzb? or ?0101xxxzb?. the device?s addressing, as implemented, uses sma2 an d sma1 and includes a hi-z state for the sma2 address pin. therefore, the thermal sensing device supports six unique resulting addresses. to set the hi-z state for sma2, the pin must be left floating. the system should drive sma1 and sma0, and will be pulled low (if not driven) by the 10 k pull- down resistor on the processor substrate. attempting to drive either of these signals to a hi-z state would cause ambiguity in the memory device address decode, possibly resulting in the devices not responding, t hus timing out or hanging the smbus. as before, the ?z? bit is the read/write bit for the serial bus transaction. figure 6-1 shows a logical diagram of the pin connections. ta b l e 6 - 2 and ta b l e 6 - 3 describe the address pin connections and ho w they affect the addressing of the devices. note: addresses of the form ?0000xxxxb? are rese rved and should not be generated by an smbus master. also, system management software must be aware of the processor select in the address for the thermal sensing device. table 6-2. thermal sensing device smbu s addressing on the dual-core intel ? itanium ? processor 9000 an d 9100 series address (hex) upper address 1 notes: 1. upper address bits are decoded in conjunction with the select pins. processor select 8-bit address word on serial bus sma2 sma1 b[7:0] 3xh 0011 0 0 0011000xb 0011 0 1 0011010xb 5xh 0101 z 2 2. a tri-state or ?z? state on this pin is achieved by leaving this pin unconnected. 0 0101001xb 0101 z b 1 0101011xb 9xh 1001 1 0 1001100xb 1001 1 1 1001110xb
82 dual-core intel ? itanium ? processor 9000 and 9100 series datasheet system management feature specifications 6.2 processor information rom an electrically programmed read-only memo ry (rom) provides information about the processor. the checksum bits for each cate gory provide error correction and serve as a mechanism to check whether data is corrupted or not. this information is permanently write-protected. ta b l e 6 - 4 shows the data fields and formats provided in the memory. note: the data, in byte format, is wr itten and read serially, with the most significant bit first. table 6-3. eeprom smbus addre ssing on the dual-core intel ? itanium ? processor 9000 and 9100 series address (hex) upper address 1 notes: 1. although this addressing scheme is targeted for up to four-way mp systems, more processors can be supported by using a multiplexed (or se parate) smbus implementation. processor select memory device select read/ write device addressed bits 7?4 (sma1) bit 3 (sma0) bit 2 bit 1 bit 0 a0h/a1h 1010 0 0 0 x scratch eeprom 1 a2h/a3h 1010 0 0 1 x processor information rom 1 a4h/a5h 1010 0 1 0 x scratch eeprom 2 a6h/a7h 1010 0 1 1 x processor information rom 2 a8h/a9h 1010 1 0 0 x scratch eeprom 3 aah/abh 1010 1 0 1 x processor information rom 3 ach/adh 1010 1 1 0 x scratch eeprom 4 aeh/afh 1010 1 1 1 x processor information rom 4 table 6-4. processor information rom format (sheet 1 of 3) offset/ section # of bits function notes examples header 00h 8 data format revision two 4-bit hex digits start with 00h 01h 16 eeprom size size in bytes (msb first) use a decimal to hex transfer; 128 bytes = 0080h: ? 02h[7:4] = 0000 ? 02h[3:0] = 0000 ? 01h[7:4] = 1000 ? 01h[3:0] = 0000 03h 8 processor data address byte pointer, 00h if not present 0eh 04h 8 processor core address byte pointer, 00h if not present 17h 05h 8 processor cache address byte pointer, 00h if not present 28h 06h 8 processor data address byte pointer, 00h if not present 37h 07h 8 part number data address byte pointer, 00h if not present 3eh 08h 8 thermal reference data address byte pointer, 00h if not present 63h 09h 8 feature data address byte pointer, 00h if not present 67h 0ah 8 other data address byte pointer, 00h if not present 7ah
dual-core intel ? itanium ? processor 9000 and 9100 series datasheet 83 system management feature specifications 0bh 16 reserved reserved for future use 0000h 0dh 8 checksum 1 byte checksum add up by byte and take 2?s complement. processor 0eh 48 s-spec number six 8-bit ascii characters s-spec number of s123 would be: ? 13h = 00h ? 12h = 00h ? 11h = ?3? ? 10h = ?2? ?0fh = ?1? ?0eh = ?s? 14h 2 sample/production 00b = sample only (msb first) 00000001b = production 15h 8 reserved reserved for future use 00h 16h 8 checksum 1 byte checksum add up by byte and take 2?s complement. core 17h 8 architecture revision from cpuid 1 ta k e n f r o m cpuid[3].archrev. 18h 8 processor core family from cpuid taken from cpuid[3].family. 19h 8 processor core model from cpuid taken from cpuid[3].model. 1ah 8 processor core stepping from cpuid taken from cpuid[3].revision. 1bh 24 reserved reserved for future use 000000h 1eh 16 maximum core frequency four 4-bit hex digits (in mhz) 1 ghz = 1000h 2 20h 12 maximum system bus frequency three 4-bit hex digits (in mhz) 200 mhz = 200h 1 22h 16 core voltage id voltage in four 4-bit hex digits (in mv) 1500 mv = 1500h 1 24h 8 core voltage tolerance, high edge finger tolerance in mv, + two 4-bit hex digits 1.5% = 22 mv = 22h 1 25h 8 core voltage tolerance, low edge finger tolerance in mv, ? two 4-bit hex digits 1.5% = 22 mv = 22h 1 26h 8 reserved reserved for future use 00h 27h 8 checksum 1 byte checksum add up by byte and take 2?s complement. cache 28h 32 reserved reserved for future use 00000000h 2ch 16 cache size four 4-bit hex digits (in kbytes) 3072 kbytes = 3072h 1,3 2eh 64 reserved reserved for future use x0h 36h 8 checksum 1 byte checksum package 37h 32 package revision four 8-bit ascii characters ne: ? 37h = n ? 38h = e ? 39h = 0 ?3ah = 0 3bh 2 substrate revision software id 2-bit revision number 00 table 6-4. processor informat ion rom format (sheet 2 of 3) offset/ section # of bits function notes examples
84 dual-core intel ? itanium ? processor 9000 and 9100 series datasheet system management feature specifications 3ch 8 reserved reserved for future use 00h 3dh 8 checksum 1 byte checksum add up by byte and take 2?s complement part numbers 3eh 56 processor part number seven 8-bit ascii characters 80549kc ?3eh = ?8? ?3fh = ?0? ? 40h = ?5? ? 41h = ?4? ? 42h = ?2? ? 43h = ?k? ? 44h = ?c? 45h 64 processor electronic signature 64-bit identification number may have padded zeros 4dh 168 reserved reserved for future use x0h 62h 8 checksum 1 byte checksum add up by byte and take 2?s complement thermal reference 63h 8 upper temp reference byte hex value of thermal upper temp limit default = 92 = 5ch 64h 8 thermal calibration offset byte present number of degrees in error () will be set per part and expected to be ~ +12c 65h 8 reserved reserved for future use 00h 66h 8 checksum 1 byte checksum add up by byte and take 2?s complement. features 67h 32 ia-32 processor core feature flags from 32 bit cpuid 4387fbffh 6bh 64 reserved reserved (processor core feature flags implemented in the itanium ? processor family) 0000 0000 6380 811bh 73h 32 processor feature flags all others are reserved: [9] = demand based switching enabled [8] = core level lockstep enabled [7] = socket level lockstep enabled [6] = dual core enabled [5] = hyper-threading enabled [4] = upper temp reference byte [3] = thermal calibration offset byte present [2] = scratch eerpom present [1] = core vid present 1 indicates eeprom data for specified field is valid. 77h 4 number of devices in tap chain one 4-bit hex digit 2h for dual-core processor 78h 4 reserved reserved for future use 0h 79h 8 checksum 1 byte checksum add up by byte and take 2?s complement. other 7ah 16 reserved reserved for future use 0000h table 6-4. processor information rom format (sheet 3 of 3) offset/ section # of bits function notes examples
dual-core intel ? itanium ? processor 9000 and 9100 series datasheet 85 system management feature specifications 6.3 scratch eeprom also available on the smbus interface on the processor is an eeprom which may be used for other data at the system vendor?s discretion (intel will not be using the scratch eeprom). the data in this eeprom, once programmed, can be write-protected by asserting the active-high smwp signal. this signal has a weak pull-down (10 k ) to allow the eeprom to be programmed in system s with no implementation of this signal. 6.4 processor information rom and scratch eeprom supported smbus transactions the processor information rom and scratch eeprom responds to three of the smbus packet types: current address read, random address read, and sequential read. ta b l e 6 - 5 shows the format of the current addr ess read smbus packet. the internal address counter keeps track of the address accessed during the last read or write operation, incremented by one. address ?roll ov er? during reads is from the last byte of the last eight byte page to the first byte of the first page. ?roll over? during writes is from the last byte of the current eight byte page to the first byte of the same page. ta b l e 6 - 6 shows the format of the random read smbus packet. the write with no data loads the address desired to be read. se quential reads may begin with a current address read or a random address read. af ter the smbus host controller receives the data word, it responds with an acknowledge. this will continue until the smbus host controller responds with a negative acknowledge and a stop. ta b l e 6 - 7 shows the format of the byte write smbus packet. the page write operates the same way as the byte write, except that the smbus host controller does not send a stop after the first data byte and ac knowledge. the scratch eeprom internally increments its address. the smbus host controller continues to transmit data bytes until it terminates the sequence with a stop. all data bytes will result in an acknowledge from the scratch eeprom. if more than eigh t bytes are written, the internal address will ?roll over? and the previous data will be overwritten. in ta b l e 6 - 5 through ta b l e 6 - 7 , ?s? represents the smbus start bit, ?p? represents a stop bit, ?r? represents a read, ?w? represents a wr ite bit, ?a? represents an acknowledge, and ?///? represents a negative acknowledge. the shaded bits are transmitted by the processor information rom or scratch eeprom and the bits that are not shaded are transmitted by the smbus host controller. in the tables, the data addresses indicate eight bits. the smbus host controller should transmit eight bits, but as there are only 128 addresses, the most significant bit is a don?t care. notes: 1. refer to the intel? itanium? architecture software developer?s manual for details on cpuid registers. 2. the translation is using bcd. 3. itanium 9000 and 9100 series use a hex-to-decimal conversion table 6-5. current address read smbus packet s device address r a data /// p 17 bits1 1 8 bits 1 1
86 dual-core intel ? itanium ? processor 9000 and 9100 series datasheet system management feature specifications 6.5 thermal sensing device the dual-core intel itanium processor 9000 and 9100 series thermal sensing device provides a means of acquiring thermal data from the processor. the accuracy of the thermal reading is expected to be better than 5 c. the thermal sensing device is composed of control logic, smbus interface logi c, a precision analog to digital converter, and a precision current source. the thermal sensing device drives a small current through a thermal diode located on the processor core and measures the voltage generated across the thermal diode by the current. with this information, the thermal sensing device computes a byte of temperature data. software running on the processor or on a micro-controller can use the temperature data from the thermal sensing device to thermally manage the system. the thermal sensing device provides a register with a data byte (seven bits plus sign) which contains a value corresponding to the sampled output of the thermal diode in the processor core. the value of the byte read from the thermal sensor is always higher than the actual processor core temperature; therefore, the offset from the reading needs to be subtracted to obtain an accurate reading of the processor core temperature. this data can be used in conjunction with the upper temperature reference byte (provi ded in the processor information rom) for thermal management purposes. the temperature data from the th ermal sensor can be read out digitally using an smbus read command (see section 6.6 ). the thermal sensor detects when smbus power is applied to the processo r, and resets itself at power-up. the thermal sensing device also contains alarm registers to store thermal reference threshold data. these values can be individu ally programmed on the thermal sensor. if the measured temperature equals or exceeds the alarm threshold value, the appropriate bit is set in the thermal sensing device status register, which is also brought out to the processor system bus via the thrmalert# signal (see section 6.1.1 for more details). at power-up, th e appropriate alarm register values need to be programmed into the thermal sensing device via the smbus. it is recommended that the upper thermal refe rence threshold byte (provided in the processor information rom) be used for setti ng the upper threshold value in the alarm register. to account for the offset inherent in the thermal sensing device reading, the actual programmed value of the upper threshold value in the alarm register should be the sum of the upper thermal reference threshold byte and the thermal calibration offset byte (both provided in the pirom). when polling the thermal sensing device on the processor to read the processor temperatures, it is recommended that the polling frequency be every 0.5 to 1 second. table 6-6. random address read smbus packet s device address w a data address as device address r a data /// p 17 bits1 18 bits 11 7 bits 1 1 8 bits 1 1 table 6-7. byte write smbus packet s device address w a data address adata ap 17 bits0 18 bits 18 bits 11
dual-core intel ? itanium ? processor 9000 and 9100 series datasheet 87 system management feature specifications 6.6 thermal sensing device supported smbus transactions the thermal sensing device responds to five of the smbus packet types: write byte, read byte, send byte, receive byte, and aler t response address (ara). the send byte packet is used for sending one-shot commands only. the receive byte packet accesses the register commanded by the last read by te packet. if a receive byte packet was preceded by a write byte or send byte pack et more recently than a read byte packet, then the behavior is undefined. ta b l e 6 - 8 through ta b l e 6 - 1 2 diagram the five packet types. in these tables, ?s? represents the smbu s start bit, ?p? represents a stop bit, ?ack? represents an acknowledge, and ?///? represents a negative acknowledge. the shaded bits are transmitted by the thermal sensor and the unshaded bits are transmitted by the smbus host controller. ta b l e 6 - 1 3 shows the encoding of the command byte. table 6-8. write byte smbus packet saddresswrite ack command ack data ack p 17 bits 1 18 bits 18 bits 11 table 6-9. read byte smbus packet saddresswrite ack command ack s address read ack data // / p 17 bits 0 18 bits 11 7 bits 1 1 8 bits 1 1 table 6-10. send byte smbus packet saddresswrite ack command ack p 17 bits 1 18 bits 1 table 6-11. receive byte smbus packet saddressread ack data /// p 17 bits 1 1 8 bits 1 1 table 6-12. ara smbus packet sararead ack address /// p 1 0001 100 1 1 1001 1011 1 1
88 dual-core intel ? itanium ? processor 9000 and 9100 series datasheet system management feature specifications all of the commands are for reading or writ ing registers in the thermal sensor except the one-shot command (osht). the one-shot command forces the immediate start of a new voltage-to-temperature conversion cycle. if a conversion is in progress when the one-shot command is received, then the co mmand is ignored. if the thermal sensing device is in standby mode when the one-shot command is received, a conversion is performed and the sensor returns to standby mode. if the thermal sensor is in auto- convert mode and is between conversions, then the conversion rate timer resets, and the next automatic conversion takes place after a full delay elapses. please refer to section 6.7.4 for further detail on standby and auto-convert modes. the default command after reset is the reserved value (00h). after reset, receive byte packets will return invalid data until another command is sent to the thermal sensing device. 6.7 thermal sensing device registers the system management software can configure and control the thermal sensor by writing to and interacting with different registers in the thermal sensor. these registers include a thermal reference register, two thermal limit registers, a status register, a configuration register, a conversion rate re gister, and other reserved registers. the following subsections describe the registers in detail. 6.7.1 thermal reference registers the processor core and thermal sensing device internal thermal reference registers contain the thermal reference value of the thermal sensing device and the processor core thermal diodes. this value ranges from +127 to ?128 decimal and is expressed as a two?s complement, eight-bit number. these registers are saturating, that is, values above 127 are represented at 127 decimal, and values below ?128 are represented as ?128 decimal. table 6-13. command byte bit assignment register command reset state function reserved 00h n/a reserved for future use. rrt 01h n/a read processor core thermal data. rs 02h n/a read status byte (flags, busy signal). rc 03h 0000 0000 read configuration byte. rcr 04h 0000 0010 read conversion rate byte. reserved 05h 0111 1111 reserved for future use. reserved 06h 1100 1001 reserved for future use. rrhl 07h 0111 1111 read processor core thermal diode t high limit. rrll 08h 1100 1001 read processor core thermal diode t low limit. wc 09h n/a write configuration byte. wcr 0ah n/a write conversion rate byte. reserved 0bh n/a reserved for future use. reserved 0ch n/a reserv ed for future use. wrhl 0dh n/a write processor core thermal diode t high limit. wrll 0eh n/a write processor core thermal diode t low limit. osht 0fh n/a one shot command (use send byte packet). reserved 10h ? ffh n/a reserved for future use.
dual-core intel ? itanium ? processor 9000 and 9100 series datasheet 89 system management feature specifications 6.7.2 thermal limit registers the thermal sensing device has two thermal limit registers; they define high and low limits for the processor core thermal diode. the encoding for these registers is the same as for the thermal reference registers. if the diode thermal value equals or exceeds one of its limits, then its alarm bit in the status register is triggered. this indication is also brought out to the processor system bus via the thrmalert# signal. 6.7.3 status register the status register shown in ta b l e 6 - 1 4 indicates which (if any) of the thermal value thresholds have been exceeded. it also indicates if a conversion is in progress or if an open circuit has been detected in the processor core thermal diode connection. once set, alarm bits stay set until they are cleared by a status register read. a successful read to the status register will clear any alarm bits that may have been set, unless the alarm condition persists. note that the thrm alert# interrupt signal is latched and is not automatically cleared when the status flag bit is cleared. the latch is cleared by sending the alert response address (0001100) on the smbus. 6.7.4 configuration register the configuration register controls the oper ating mode (standby vs. auto-convert) of the thermal sensing device. ta b l e 6 - 1 5 shows the format of the configuration register. if the run/stop bit is set (high) then the thermal sensing device immediately stops converting and enters standby mode. the thermal sensing device will still perform analog-to-digital conversions in standby mode when it receives a one-shot command. if the run/stop bit is clear (low) then the thermal sensor enters auto-conversion mode. the thermal sensing device starts operating in free running mode, auto- converting at 0.25 hz after power-up. table 6-14. thermal sensin g device status register bit name function 7 (msb) busy a one indicates that the device?s an alog to digital converter is busy converting. 6 reserved reserved for future use. 5 reserved reserved for future use. 4 rhigh a one indicates that the processor core thermal diode high temperature alarm has been activated. 3 rlow a one indicates that the processor co re thermal diode low temperature alarm has been activated. 2 open a one indicates an open fault in the connection to the processor core diode. 1 reserved reserved for future use. 0 (lsb) reserved reserved for future use. table 6-15. thermal sensing de vice configuration register bit name reset state function 7 (msb) reserved 0 reserved for future use. 6 run/stop 0 standby mode control bit. if high, the device immediately stops converting, and enters standby mode. if low, the device converts in either one-shot or timer mode. 5?0 reserved 0 reserved for future use.
90 dual-core intel ? itanium ? processor 9000 and 9100 series datasheet system management feature specifications 6.7.5 conversion rate register the contents of the conversion rate regi ster determine the nominal rate at which analog-to-digital conversions happen when the thermal sensing device is in auto- convert mode. ta b l e 6 - 1 6 shows the mapping between conversion rate register values and the conversion rate. as indicated in ta b l e 6 - 1 6 , the conversion rate register is set to its default state of 02h (0.25 hz nominally) when the thermal sensing device is powered-up. there is a 25% error tolerance between the conversion rate indicated in the conversion rate register and the actual conversion rate. table 6-16. thermal sensing devi ce conversion rate register register contents conversion rate (hz) 00h 0.0625 01h 0.125 02h 0.25 03h 0.5 04h 1 05h 2 06h 4 07h 8 08h to ffh reserved for future use
dual-core intel ? itanium ? processor 9000 and 9100 series datasheet 91 signals reference a signals reference this appendix provides an alphabetical lis ting of all dual-core intel itanium 9000 and 9100 series processor system bus signals. the tables at the end of this appendix summarize the signals by direction: output, input, and i/o. for a complete pinout listing including processor specific pins, please refer to chapter 3, ?pinout specifications.? a.1 alphabetical signals reference a.1.1 a[49:3]# (i/o) the address (a[49:3]#) signals, with byte enables, define a 2 50 byte physical memory address space. when ads# is active, these pi ns transmit the address of a transaction. these pins are also used to transmit other transaction related information such as transaction identifiers and external functions in the cycle following ads# assertion. these signals must connect the appropriate pi ns of all agents on the processor system bus. the a[49:27]# signals are parity-protected by the ap1# parity signal, and the a[26:3]# signals are parity-protected by the ap0# parity signal. on the active-to-inactive transition of reset#, the processors sample the a[49:3]# pins to determine their power-on configuration. a.1.2 a20m# (i) a20m# is no connect and is ignored in the processor system environment. a.1.3 ads# (i/o) the address strobe (ads#) signal is asserted to indicate the validity of the transaction address on the a[49:3]#, req[5:0]#, ap[1:0]# and rp#pins. all bus agents observe the ads# activation to begin parity checking, protocol checking, address decode, internal snoop, or deferred reply id ma tch operations associated with the new transaction. a.1.4 ap[1:0]# (i/o) the address parity (ap[1:0]#) signals can be driven by the request initiator along with ads# and a[49:3]#. ap[1]# covers a[49 :27]#, and ap[0]# covers a[26:3]#. a correct parity signal is high if an even number of covered signals are low and low if an odd number of covered signals are low. this allows parity to be high when all the covered signals are high. a.1.5 asz[1:0]# (i/o) the asz[1:0]# signals are the memory address- space size signals. they are driven by the request initiator during the first request phase clock on the reqa[4:3]# pins. the asz[1:0]# signals are valid only when reqa[2:1]# signals equal 01b, 10b, or 11b, indicating a memory access transaction. the asz[1:0]# decode is defined in ta b l e a - 1 .
92 dual-core intel ? itanium ? processor 9000 and 9100 series datasheet signals reference any memory access transaction addressing a memory region that is less than 64 gb (that is, aa[49:36]# are all zeroes) must set asz[1:0]# to 01. any memory access transaction addressing a memory region that is equal to or greater than 64 gb (that is, aa[49:36]# are not all zeroes) must set asz[1:0]# to 10. all observing bus agents that support the 64 gbyte (36-bit) address space must respond to the transaction when asz[1:0]# equals 01. all observing bus agents that support larger than the 64 gbyte (36-bit) address space must respond to the transaction when asz[1:0]# equals 01 or 10. a.1.6 attr[3:0]# (i/o) the attr[3:0]# signals are the attribute si gnals. they are driven by the request initiator during the second clock of the request phase on the ab[35:32]# pins. the attr[3:0]# signals are valid for all transactions. the attr[3]# signal is reserved. the attr[2:0]# are driven based on the memory type. please refer to ta b l e a - 2 . a.1.7 bclkp/bclkn (i) the bclkp and bclkn differential clock signal s determine the bus frequency. all agents drive their outputs and latch their inputs on the differential crossing of bclkp and bclkn on the signals that are using the common clock latched protocol. bclkp and bclkn indirectly determine the in ternal clock frequency of the processor. each processor derives its internal cl ock by multiplying the bclkp and bclkn frequency by a ratio that is defined an d allowed by the power-on configuration. a.1.8 be[7:0]# (i/o) the be[7:0]# signals are the byte-enable signals for partial transactions. they are driven by the request initiator during the second request phase clock on the ab[15:8]# pins. table a-1. address space size asz[1:0]# memory address space memory access range 0 0 reserved reserved 0 1 36-bit 0 to (64 gbyte - 1) 1 0 50-bit 64 gbyte to (1 pbyte ?1) 1 1 reserved reserved table a-2. effective memo ry type signal encoding attr[2:0]# description 000 uncacheable 100 write coalescing 101 write-through 110 write-protect 111 writeback
dual-core intel ? itanium ? processor 9000 and 9100 series datasheet 93 signals reference for memory or i/o transactions, the byte-enable signals indicate that valid data is requested or being transferred on the corre sponding byte on the 128-bit data bus. be[0]# indicates that the least significant by te is valid, and be[7]# indicates that the most significant byte is valid. since be[7:0]# specifies the validity of only 8 bytes on the 16 byte wide bus, a[3]# is used to determ ine which half of the data bus is validated by be[7:0]#. for special transactions ((reqa[5:0]# = 001000b) and (reqb[1:0]# = 01b)), the be[7:0]# signals carry special cycle encodings as defined in ta b l e a - 3 . all other encodings are reserved. for deferred reply transactions, be[7:0]# signals are reserved. the defer phase transfer length is always the same length as that specified in the request phase except the bus invalidate line (bil) transaction. a bil transaction may return one cache line (128 bytes). a.1.9 berr# (i/o) the bus error (berr#) signal can be asserted to indicate a recoverable error with global mca. berr# assertion conditions are configurable at the system level. configuration options enable berr# to be driven as follows: ? asserted by the requesting ag ent of a bus transaction after it observes an internal error. ? asserted by any bus agent when it observes an error in a bus transaction. when the bus agent samples an asserted berr# signal and berr# sampling is enabled, the processor enters a machine check handler. berr# is a wired-or signal to allow multiple bus agents to drive it at the same time. table a-3. special transaction encoding on byte enables special transaction byte enables[7:0]# nop 0000 0000 shutdown 0000 0001 flush (invd) 0000 0010 halt 0000 0011 sync (wbinvd) 0000 0100 reserved 0000 0101 stopgrant acknowledge 0000 0110 reserved 0000 0111 xtpr update 0000 1000
94 dual-core intel ? itanium ? processor 9000 and 9100 series datasheet signals reference a.1.10 binit# (i/o) if enabled by configuration, th e bus initialization (binit#) signal is asserted to signal any bus condition that prevents reliable future operation. if binit# observation is enabled during power-on configuration, and binit# is sampled asserted, all bus state machines are reset. all agents reset their rotating ids for bus arbitration to the same state as that after reset, and internal count information is lost. the l2 and l3 caches are not affected. if binit# observation is disabled during power-on configuration, binit# is ignored by all bus agents with the exception of the prio rity agent. the priority agent must handle the error in a manner that is appropriate to the system architecture. binit# is a wired-or signal. a.1.11 bnr# (i/o) the block next request (bnr#) signal is us ed to assert a bus stall by any bus agent that is unable to accept new bus transactio ns to avoid an internal transaction queue overflow. during a bus stall, the current bus owner cannot issue any new transactions. since multiple agents might need to request a bus stall at the same time, bnr# is a wired-or signal. in order to avoid wired-or glitches associated with simultaneous edge transitions driven by multiple drivers, bnr# is asserted and sampled on specific clock edges. a.1.12 bpm[5:0]# (i/o) the bpm[5:0]# signals are system support si gnals used for inserting breakpoints and for performance monitoring. they can be conf igured as outputs from the processor that indicate programmable counters used for monitoring performance, or inputs from the processor to indicate the status of breakpoints. a.1.13 bpri# (i) the bus priority-agent request (bpri#) signal is used by the priority agent to arbitrate for ownership of the system bus. observing bpri# asserted causes all other agents to stop issuing new requests, unless such requests are part of an ongoing locked operation.the priority agent keeps bpri# asserted until all of its requests are completed, then releases the bus by deasserting bpri#. a.1.14 br[0]# (i/o) and br[3:1]# (i) br[3:0]# are the physical bus request pins that drive the breq[3:0]# signals in the system. the breq[3:0]# signals are interconnected in a rotating manner to individual processor pins. ta b l e a - 4 and ta b l e a - 4 give the rotating interconnection between the processor and bus signals for both the 4p and 2p system bus topologies.
dual-core intel ? itanium ? processor 9000 and 9100 series datasheet 95 signals reference during power-on configuration, the priority agent must assert the br[0]# bus signal. all symmetric agents sample their br[3:0]# pins on asserted-to-deasserted transition of reset#. the pin on which the agent sample s an asserted level determines its agent id. all agents then configure their pins to match the appropriate bus signal protocol as shown in ta b l e a - 6 . a.1.15 breq[3:0]# (i/o) the breq[3:0]# signals are the symmetric agent arbitration bus signals (called bus request). a symmetric agent n arbitrates for the bus by asserting its breq n # signal. agent n drives breq n # as an output and receives the remaining breq[3:0]# signals as inputs. the symmetric agents support distribute d arbitration based on a round-robin mechanism. the rotating id is an internal state used by all symmetric agents to track the agent with the lowest priority at the next arbitration event. at power-on, the rotating id is initialized to three, allowing agent 0 to be the highest priority symmetric agent. after a new arbitration event, the rota ting id of all symmetric agents is updated to the agent id of the symmetric owner. this update gives the new symmetric owner lowest priority in the next arbitration event. a new arbitration event occurs either when a symmetric agent asserts its breq n # on an idle bus (all breq[3:0]# previously de asserted), or the current symmetric owner deasserts breqn# to release the bus ownership to a new bus owner n . on a new arbitration event, all symmetric agents si multaneously determine the new symmetric owner using breq[3:0]# and the rotating id. the symmetric owner can park on the bus (hold the bus) provided that no other symmetric agent is requesting its use. the symmetric owner parks by keeping its breq n # signal asserted. on sampling breqn# asserted by another symmetric agent, the symmetric owner deasserts breq n # as soon as possible to release the bus. a symmetric owner stops issuing new requests that are not part of an existing locked op eration on observing bpri# asserted. table a-4. br0# (i/o), br1#, br2#, br3# signals for 4p rotating interconnect bus signal agent 0 pins agent 1 pins agent 2 pins agent 3 pins breq[0]# br[0]# br[3]# br[2]# br[1]# breq[1]# br[1]# br[0]# br[3]# br[2]# breq[2]# br[2]# br[1]# br[0]# br[3]# breq[3]# br[3]# br[2]# br[1]# br[0]# table a-5. br0# (i/o), br1#, br2#, br3# signals for 2p rotating interconnect bus signal agent 0 pins agent 3 pins breq[0]# br[0]# br[1]# breq[1]# br[1]# br[0]# breq[2]# not used not used breq[3]# not used not used table a-6. br[3:0]# signals and agent ids pin sampled asserted on reset# arbitration id agent id reported br[0]# 0 0 br[3]# 1 2 br[2]# 2 4 br[1]# 3 6
96 dual-core intel ? itanium ? processor 9000 and 9100 series datasheet signals reference a symmetric agent can deassert breq n # before it becomes a symmetric owner. a symmetric agent can reassert breq n # after keeping it deasserted for one clock. a.1.16 ccl# (i/o) ccl# is the cache cleanse signal. it is driven on the second clock of the request phase on the exf[2]#/ab[5]# pin. ccl# is asserted for memory write transaction to indicate that a modified line in a processor may be written to memory without being invalidated in its caches. a.1.17 cpupres# (o) cpupres# can be used to detect the presence of a processor in a socket. a ground indicates that a processor is installed, while an open indicates that a processor is not installed. a.1.18 d[127:0]# (i/o) the data (d[127:0]#) signals provide a 128- bit data path between various system bus agents. partial transfers require one data tran sfer clock with valid data on the byte(s) indicated by asserted byte enables be[7:0]# and a[3]#. data signals that are not valid for a particular transfer must still have correct ecc (if data bus error checking is enabled). the data driver asserts drdy# to indicate a valid data transfer. a.1.19 d/c# (i/o) the data/code (d/c#) signal is used to in dicate data (1) or code (0) on reqa[1]#, only during memory read transactions. a.1.20 dbsy# (i/o) the data bus busy (dbsy#) signal is assert ed by the agent that is responsible for driving data on the system bus to indicate that the data bus is in use. the data bus is released after dbsy# is deasserted. dbsy# is replicated three time s to enable partitioning of the data paths in the system agents. this copy of the data bus busy signal (dbsy#) is an input as well as an output. a.1.21 dbsy_c1# (o) dbsy# is a copy of the data bus busy signal . this copy of the data bus busy signal (dbsy_c1#) is an output only. a.1.22 dbsy_c2# (o) dbsy# is a copy of the data bus busy signal . this copy of the data bus busy signal (dbsy_c2#) is an output only. a.1.23 defer# (i) the defer# signal is asserted by an agent to indicate that the transaction cannot be guaranteed in-order completion . assertion of defer# is normally the responsibility of the priority agent.
dual-core intel ? itanium ? processor 9000 and 9100 series datasheet 97 signals reference a.1.24 den# (i/o) the defer enable (den#) signal is driven on the bus on the second clock of the request phase on the ab[4]# pin. den# is asserted to indicate that the transaction can be deferred by the responding agent. a.1.25 dep[15:0]# (i/o) the data bus ecc protection (dep[15:0]#) signals provide optional ecc protection for data bus (d[127:0]#). they are driven by the agent responsible for driving d[127:0]#. during power-on configuration, bus agents can be enabled for either ecc checking or no checking. the ecc error correcting code can detect and correct single-bit errors and detect double-bit or nibble errors. a.1.26 dhit# (i) the deferred hit (dhit#) signal is driven du ring the deferred phase by the deferring agent. for read transactions on the bus dhit# returns the final cache status that would have been indicated on hit# for a transaction which was not deferred. did[9:0]# (i/ o) did[9:0]# are deferred identifier signals. the requesting agent transfers these signals by using a[25:16]#. they are transferred on ab[25:16]# during the second clock of the request phase on all transactions, but ab[20:16]# is only defined for deferrable transactions (den# asserted). did[9:0]# is also transferred on aa[25:16]# during the first clock of the request phase for deferred reply transactions. the deferred identifier defines the token supplied by the requesting agent. did[9]# and did[8:5]# carry the agent identifiers of the requesting agents (always valid) and did[4:0]# carry a transaction identifier associated with the request (valid only with den# asserted). this configur ation limits the bus specification to 32 logical bus agents with each one of the bus agents capable of making up to 32 requests. ta b l e a - 7 shows the did encodings. did[9]# indicates the agent type. symmetric agents use 0. priority agents use 1. did[8:5]# indicates the agent id. symmetric agents use their arbitration id. did[4:0]# indicates the transaction id for an agent. the transaction id must be unique for all deferrable transactions issued by an agent which have not reported their snoop results. the deferred reply agent transmits the did[9:0]# (ab[25:16]#) signals received during the original transaction on the aa[25:16]# signals during the deferred reply transaction. this process enables the original requesting agent to make an identifier match with the original request that is awaiting completion. table a-7. did[9:0]# encoding did[9]# did[8:5]# did[4:0]# agent type agent id[3:0] transaction id[4:0]
98 dual-core intel ? itanium ? processor 9000 and 9100 series datasheet signals reference a.1.27 dps# (i/o) the deferred phase enable (dps#) signal is driven to the bus on the second clock of the request phase on the ab[3]# pin. dps# is asserted if a requesting agent supports transaction completion using the deferred phas e. a requesting agent that supports the deferred phase will always asse rt dps#. a requesting agent that does not support the deferred phase will always deassert dps#. a.1.28 drdy# (i/o) the data ready (drdy#) signal is asserted by the data driver on each data transfer, indicating valid data on the data bus. in a multi-cycle data transfer, drdy# can be deasserted to insert idle clocks. drdy# is replicated three times to enable partitioning of data paths in the system agents. this copy of the data ready signal (drdy#) is an input as well as an output. a.1.29 drdy_c1# (o) drdy# is a copy of the data ready signal. this copy of the data phase data-ready signal (drdy_c1#) is an output only. a.1.30 drdy_c2# (o) drdy# is a copy of the data ready signal. this copy of the data phase data-ready signal (drdy_c2#) is an output only. a.1.31 dsz[1:0]# (i/o) the data size (dsz[1:0]#) signals are transferred on reqb[4:3]# signals in the second clock of the request phase by the requesting agent. the dsz[1:0]# signals define the data transfer capability of the re questing agent. for the processor, dsz# = 01, always. a.1.32 exf[4:0]# (i/o) the extended function (exf[4:0]#) signals ar e transferred on the a[7:3]# pins by the requesting agent during the second clock of the request phase. the signals specify any special functional requirement associated wi th the transaction based on the requestor mode or capability. the signals are defined in ta b l e a - 8 . table a-8. extended function signals extended function signal signal name alias function exf[4]# reserved reserved exf[3]# splck#/fcl# split lock / flush cache line exf[2]# own#/ccl# memory update not needed / cache cleanse exf[1]# den# defer enable exf[0]# dps# deferred phase supported
dual-core intel ? itanium ? processor 9000 and 9100 series datasheet 99 signals reference a.1.33 fcl# (i/o) the flush cache line (fcl#) signal is driven to the bus on the second clock of the request phase on the a[6]# pin. fcl# is asserted to indicate that the memory transaction is initiated by the global flush cache ( fc ) instruction. a.1.34 ferr# (o) the ferr# signal may be asserted to indicate a processor detected error when ierr mode is enabled. if ierr mode is disabled, th e ferr# signal will not be asserted in the processor system environment. a.1.35 gseq# (i) assertion of the guaranteed sequentiality (g seq#) signal indicates that the platform guarantees completion of the transaction without a retry while maintaining sequentiality. a.1.36 hit# (i/o) and hitm# (i/o) the snoop hit (hit#) and hit modified (hitm#) signals convey transaction snoop operation results. any bus agent can assert both hit# and hitm# together to indicate that it requires a snoop stall. the stall can be continued by reasserting hit# and hitm# together. a.1.37 id[9:0]# (i) the transaction id (id[9:0]#) signals are driven by the deferring agent. the signals in the two clocks are referenced ida[9:0]# and idb[9:0]#. during both clocks, id[9:0]# signals are protected by the ip0# parity sign al for the first clock, and by the ip[1]# parity signal on the second clock. ida[9:0]# returns the id of the deferred transaction which was sent on ab[25:16]# (did[9:0]#). a.1.38 ids# (i) the id strobe (ids#) signal is asserted to in dicate the validity of id[9:0]# in that clock and the validity of dhit# and ip[1:0]# in the next clock. a.1.39 ignne# (i) ignne# is no connect and is ignored in the processor system environment. a.1.40 init# (i) the initialization (init#) signal triggers an unmasked interrupt to the processor. init# is usually used to break into hanging or idle processor states. semantics required for platform compatibility are supplied in the pal firmware interrupt service routine.
100 dual-core intel ? itanium ? processor 9000 and 9100 series datasheet signals reference a.1.41 int (i) int is the 8259-compatible interrupt request signal which indicates that an external interrupt has been generated. the interrupt is maskable. the processor vectors to the interrupt handler after the current instruction execution has been completed. an interrupt acknowledge transaction is generate d by the processor to obtain the interrupt vector from the interrupt controller. the lint[0] pin can be software configured to be used either as the int signal or another local interrupt. a.1.42 ip[1:0]# (i) the id parity (ip[1:0]#) signals are driven on the second clock of the deferred phase by the deferring agent. ip0# protects the ida[9:0]# and ids# signals for the first clock, and ip[1]# protects the idb[9:2, 0]# and ids# signals on the second clock. a.1.43 len[2:0]# (i/o) the data length (len[2:0]#) signals are tr ansmitted using reqb[2:0]# signals by the requesting agent in the second clock of request phase. len[2:0]# defines the length of the data transfer requested by the requesting agent as shown in ta b l e a - 9 . the len[2:0]#, hitm#, and rs[2:0]# signals together define the length of the actual data transfer. a.1.44 lint[1:0] (i) lint[1:0] are local interrupt signals. these pins are disabled after reset#. lint[0] is typically software configured as int, an 8259-compatible maskable interrupt request signal. lint[1] is typically software config ured as nmi, a non-maskable interrupt.both signals are asynchronous inputs. a.1.45 lock# (i/o) lock# is no connect and is ignored in the processor system environment. table a-9. length of data transfers len[2:0]# length 000 0 ? 8 bytes 001 16 bytes 010 32 bytes 011 64 bytes 100 128 bytes 101 reserved 110 reserved 111 reserved
dual-core intel ? itanium ? processor 9000 and 9100 series datasheet 101 signals reference a.1.46 nmi (i) the nmi signal is the non-maskable interrupt signal. asserting nmi causes an interrupt with an internally supplied vector value of 2. an external interrupt-acknowledge transaction is not generated. if nmi is asse rted during the execution of an nmi service routine, it remains pending and is recogniz ed after the eoi is executed by the nmi service routine. at most, one assertion of nmi is held pending. nmi is rising-edge sensitive. recognition of nmi is guaranteed in a specific clock if it is asserted synchronously and meets the setup and hold times. if asserted asynchronously, asserted and deasserted pulse widths of nmi must be a minimum of two clocks.this signal must be software configured to be used either as nmi or as another local interrupt (lint1 pin). a.1.47 own# (i/o) the guaranteed cache line ownership (own#) signal is driven to the bus on the second clock of the request phase on the ab[5]# pin. own# is asserted if cache line ownership is guaranteed. this allows a me mory controller to ignore memory updates due to implicit writebacks. a.1.48 pmi# (i) the platform management interrupt (pmi#) signal triggers the highest priority interrupt to the processor. pmi# is usually used by the system to trigger system events that will be handled by pl atform specific firmware. a.1.49 pwrgood (i) the power good (pwrgood) signal must be deasserted (l) during power-on, and must be asserted (h) after reset# is first asserted by the system. a.1.50 req[5:0]# (i/o) the req[5:0]# are the request command sign als. they are asserted by the current bus owner in both clocks of the request phase. in the first clock, the reqa[5:0]# signals define the transaction type to a level of detail that is sufficient to begin a snoop request. in the second clock, reqb[5:0]# signals carry additional information to define the complete transaction type. reqb[4:3]# signals transmit dsz[1:0]# or the data transfer information of the requestor for transactions that involve data transfer. reqb[2:0]# signals transmit len[2:0]# (the da ta transfer length information). in both clocks, req[5:0]# and ads# are protected by parity rp#. all receiving agents observe the req[5:0]# signals to determine the transaction type and participate in the transaction as necessary, as shown in ta b l e a - 1 0 .
102 dual-core intel ? itanium ? processor 9000 and 9100 series datasheet signals reference a.1.51 reset# (i) asserting the reset# signal resets all proc essors to known states and invalidates all caches without writing back modified (m stat e) lines. reset# must remain asserted for one millisecond for a ?warm? reset; for a powe r-on reset, reset# must stay asserted for at least one millisecond after pwrgood and bclkp have reached their proper specifications. on observing asserted rese t#, all system bus agents must deassert their outputs within two clocks. a number of bus signals are sampled at the asserted-to-deasserted transition of reset# for the power-on configuration. unless its outputs are tristated during po wer-on configuration, after asserted-to- deasserted transition of reset#, the proce ssor begins program execution at the reset- vector a.1.52 rp# (i/o) the request parity (rp#) signal is driven by the requesting agent, and provides parity protection for ads# and req[5:0]#. a correct parity signal is high if an even number of covered signals are low and low if an odd number of covered signals are low. this defi nition allows parity to be high when all covered signals are high. table a-10. transaction types de fined by reqa#/reqb# signals transaction reqa[5:0]# reqb[5:0]# 5432 1 0543210 deferred reply0000 0 00xxxxx reserved 0000 0 10xxxxx interrupt acknowledge 0010 0 00dsz[1:0]#000 special transactions 0010 0 00dsz[1:0]#001 reserved 0010 0 00dsz[1:0]#01x reserved 0010 0 10dsz[1:0]#0xx interrupt 0010 0 10dsz[1:0]#100 purge tc 0010 0 10dsz[1:0]#101 reserved 0010 0 10dsz[1:0]#11x i/o read 0100 0 00dsz[1:0]#xxx i/o write 0100 0 10dsz[1:0]#xxx reserved 0110 0 x0dsz[1:0]#xxx memory read & invalidate 0 asz[1:0]# 0 1 0 0 dsz[1:0]# len[2:0]# reserved 0 asz[1:0]# 0 1 1 0 dsz[1:0]# len[2:0]# memory read 0 asz[1:0]# 1 d/c# 0 0 dsz[1:0]# len[2:0]# memory read current 1 asz[1:0]# 1 0 0 0 dsz[1:0]# len[2:0]# reserved 1 asz[1:0]# 1 1 0 0 dsz[1:0]# len[2:0]# memory write 0 asz[1:0]# 1 wsnp# 1 0 dsz[1:0]# len[2:0]# cache line replacement 1 asz[1:0]# 1 wsnp# 1 0 dsz[1:0]# 0 0 0
dual-core intel ? itanium ? processor 9000 and 9100 series datasheet 103 signals reference a.1.53 rs[2:0]# (i) the response status (rs[2:0]#) signals are driven by the responding agent (the agent responsible for completion of the transaction). a.1.54 rsp# (i) the response parity (rsp#) signal is driven by the responding agent (the agent responsible for completion of the current tran saction) during assertion of rs[2:0]#, the signals for which rsp# provides parity protection. a correct parity signal is high if an even number of covered signals are low and low if an odd number of covered signals are low. during the idle state of rs[2:0]# (rs[2:0]#=000), rsp# is also high since it is not driven by any agent guaranteeing correct parity. a.1.55 sbsy# (i/o) the strobe bus busy (sbsy#) signal is driven by the agent transferring data when it owns the strobe bus. sbsy# holds the strobe bus before the first drdy# and between drdy# assertions for a multiple clock data transfer. sbsy# is deasserted before dbsy# to allow the next data transfer agent to predrive the strobes before the data bus is released. sbsy# is replicated three times to enable partitioning of data paths in the system agents. this copy of the strobe bus busy signal (sbsy#) is an input as well as an output. a.1.56 sbsy_c1# (o) sbsy# is a copy of the strobe bus busy signal . this copy of the strobe bus busy signal (sbsy_c1#) is an output only. a.1.57 sbsy_c2# (o) sbsy# is a copy of the strobe bus busy signal . this copy of the strobe bus busy signal (sbsy_c2#) is an output only. a.1.58 splck# (i/o) the split lock (splck#) signal is driven in the second clock of the request phase on the ab[6]# pin of the first transaction of a lock ed operation. it is driven to indicate that the locked operation will consist of four locked transactions. a.1.59 stbn[7:0]# and stbp[7:0]# (i/o) stbp[7:0]# and stbn[7:0]# (and drdy#) are us ed to transfer data at the 2x transfer rate in lieu of bclkp. they are driven by the data transfer agent with a tight skew relationship with respect to its corresponding bus signals, and are used by the receiving agent to capture valid data in its latches. this functions like an independent double frequency clock constructed from a falling e dge of either stbp[7:0]# or stbn[7:0]#. the data is synchronized by drdy#. each strobe pair is associated with 16 data bus signals and two ecc signals as shown in ta b l e a - 1 1 .
104 dual-core intel ? itanium ? processor 9000 and 9100 series datasheet signals reference a.1.60 tck (i) the test clock (tck) signal provides the cl ock input for the ieee 1149.1 compliant tap. a.1.61 tdi (i) the test data in (tdi) signal transfers serial test data into the processor. tdi provides the serial input needed for ieee 1149.1 compliant tap. a.1.62 tdo (o) the test data out (tdo) signal transfers serial test data out from the processor. tdo provides the serial output needed for ieee 1149.1 compliant tap. a.1.63 thrmtrip# (o) the thermal trip (thrmtrip#) signal protects the processor from catastrophic overheating by use of an internal thermal sensor. this sensor is set well above the normal operating temperature to ensure that th ere are no false trips. data will be lost if the processor goes into thermal trip (signaled to the system by the assertion of the thrmtrip# signal). once thrmtrip# is assert ed, the platform must assert reset# to protect the physical integrity of the processor. a.1.64 thrmalert# (o) thrmalert# is asserted when the measured temperature from the processor thermal diode equals or exceeds the temperature threshold data programmed in the high-temp (thigh) or low-temp (tlow) registers on the sensor. this signal can be used by the platform to implement thermal regulation features. a.1.65 tms (i) the test mode select (tms) signal is an ieee 1149.1 compliant tap specification support signal used by debug tools. a.1.66 tnd# (i/o) the tlb purge not done (tnd#) signal is asserted to delay completion of a tlb purge instruction, even after the tlb purge tr ansaction completes on the system bus. table a-11. stbp[7:0]# and stbn[7:0]# associations strobe bits data bits ecc bits stbp[7]#, stbn[7]# d[127:112]# dep[15:14]# stbp[6]#, stbn[6]# d[111:96]# dep[13:12]# stbp[5]#, stbn[5]# d[95:80]# dep[11:10]# stbp[4]#, stbn[4]# d[79:64]# dep[9:8]# stbp[3]#, stbn[3]# d[63:48]# dep[7:6]# stbp[2]#, stbn[2]# d[47:32]# dep[5:4]# stbp[1]#, stbn[1]# d[31:16]# dep[3:2]# stbp[0]#, stbn[0]# d[15:0]# dep[1:0]#
dual-core intel ? itanium ? processor 9000 and 9100 series datasheet 105 signals reference a.1.67 trdy# (i) the target ready (trdy#) signal is asserted by the target to indicate that it is ready to receive a write or implicit writeback data transfer. a.1.68 trst# (i) the tap reset (trst#) signal is an ieee 1 149.1 compliant tap support signal used by debug tools. a.1.69 wsnp# (i/o) the write snoop (wsnp#) signal indicates th at snooping agents will snoop the memory write transaction a.2 signal summaries ta b l e a - 1 2 through ta b l e a - 1 5 list attributes of the processor output, input, and i/o signals. table a-12. output signals name active level clock signal group cpupres# low ? platform dbsy_c1# low bclkp data dbsy_c2# low bclkp data drdy_c1# low bclkp data drdy_c2# low bclkp data ferr# low asynchronous pc compatibility, ierr mode sbsy_c1# low bclkp data sbsy_c2# low bclkp data tdo high tck tap thrmtrip# low asynchronous error thrmalert# low asynchronous error table a-13. input signals (sheet 1 of 2) name active level clock signal group qualified bpri# low bclkp arbitration always br1# low bclkp arbitration always br2# low bclkp arbitration always br3# low bclkp arbitration always bclkp high ? control always bclkn high ? control always d/c# low bclkp system bus request phase (mem rd) defer# low bclkp snoop snoop phase dhit# low bclkp system bus ids#+1 gseq# low bclkp snoop snoop phase
106 dual-core intel ? itanium ? processor 9000 and 9100 series datasheet signals reference id[9:0]# low bclkp defer ids#, ids#+1 ids# low bclkp defer always init# low asynch exec control always 1 int (lint0) high asynch exec control ip[1:0]# low bclkp system bus ids#+1 nmi (lint1) high asynch exec control reset# low bclkp control always rs[2:0]# low bclkp response always rsp# low bclkp response always pmi# low asynch exec control pwrgood high asynch control ? tck high ? diagnostic always tdi high tck diagnostic always tms high tck diagnostic always trst# low asynch diagnostic always trdy# low bclkp response response phase notes: 1. synchronous assertion with asserted rs[2:0]# guarantees synchronization. table a-14. input/output signal s (single driver) (sheet 1 of 2) name active level clock signal group qualified a[49:3]# low bclkp request ads#, ads#+1 ads# low bclkp request always ap[1:0]# low bclkp request ads#, ads#+1 asz[1:0]# low bclkp system bus ads# attr[3:0]# low bclkp system bus ads#+1 be[7:0]# low bclkp system bus ads#+1 br0# low bclkp system bus always bpm[5:0]# low bclkp diagnostic always ccl# low bclkp system bus ads#+1 d[127:0]# low bclkp data drdy# dbsy# low bclkp data always d/c# low bclkp system bus ads# den# low bclkp system bus ads#+1 dep[15:0]# low bclkp system bus drdy# did[9:0]# low bclkp system bus ads#+1 drdy# low bclkp data always dps# low bclkp system bus ads#+1 dsz[1:0]# low bclkp system bus ads#+1 exf[4:0]# low bclkp system bus ads#+1 fcl# low bclkp system bus ads#+1 len[2:0]# low bclkp system bus ads#+1 own# low bclkp system bus ads#+1 table a-13. input signals (sheet 2 of 2) name active level clock signal group qualified
dual-core intel ? itanium ? processor 9000 and 9100 series datasheet 107 signals reference req[5:0]# low bclkp request ads#, ads#+1 rp# low bclkp request ads#, ads#+1 sbsy# low bclkp data always splck# low bclkp system bus ads#+1 stbn[7:0]# low ? data always stbp[7:0]# low ? data always wsnp# low bclkp system bus ads# table a-15. input/output signals (multiple driver) name active level clock signal group qualified bnr# low bclkp system bus always berr# low bclkp error always binit# low bclkp error always hit# low bclkp snoop snoop phase hitm# low bclkp snoop snoop phase tnd# low bclkp snoop always table a-14. input/output signal s (single driver) (sheet 2 of 2) name active level clock signal group qualified
108 dual-core intel ? itanium ? processor 9000 and 9100 series datasheet signals reference

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